The New Shape of SDR

As DSPs and FPGAs become ever more capable and general-purpose microprocessors sprout multiple and specialized cores, software defined radio (SDR) implementations are benefiting. In addition to greatly improved standard hardware components, large advances also have occurred in the processes underlying development and production of custom SOCs. All these opportunities are adding to the diversity of SDR approaches being pursued worldwide.

An FPGA can be programmed to execute a variety of algorithms at high speed. A DSP may be almost as flexible and fit better into a company’s product development flow. And, general-purpose microprocessors have the depth of compiler availability across multiple platforms that enables highly efficient program development.

On the other hand, a custom SOC can be tailored to address communications processing much more effectively than any of the other solutions. Of course, tools for programming and verifying the performance of a completely new SOC are themselves both new and proprietary.

These are just a few of the contradictions and trade-offs that characterize SDR development today. Additional factors include the specific environment in which the radio will be used; the importance of power consumption, portability, and cost; and whether the design is to replace one or more legacy systems.

A Base-Station SDR Solution

Today’s general-purpose microprocessors are fast enough to handle many types of communications algorithms as well as control functions. Vanu has taken advantage of this high-speed microprocessor technology in its Anywave^™ Base Station Subsystem (Figure 1). Power is not a major issue in most fixed-location installations, and shifting a large portion of signal processing from hardware to software has major benefits.

From a cellular-network operator’s point of view, only one equipment rack is needed regardless of the number and types of standards supported. This compares with a typical installation requiring separate hardware for each standard. And, within the Anywave rack, the only special-purpose hardware is the RF head that performs digital channelization and down-conversion in receive mode and digital up-conversion and summing in transmit mode.

Data communications with the RF head are via Gigabit Ethernet and direct fiber links. All further signal processing is done in software running on industry-standard servers. This means that the network operator can select the most appropriate computer, allowing cost savings for less stringent applications as well as the opportunity to use multiple blade servers where the highest performance is required.

For Vanu, building a totally software product involved a major testing challenge. The communications standards that have been implemented continue to change, and there are new standards periodically introduced. In addition, algorithms are continuously upgraded. All these factors are addressed by ongoing software development, but the testing implications are daunting.

To deal with the problem and improve quality by avoiding human error, a fully automated 24/7 test system was developed. As described in a paper presented at the SDR Forum Technical Conference 2006, “The continuous automated testing system…called Tinderbox, is built on the tinderbox system originally developed by the Mozilla open-source project…. In an environment of networked hosts, independent build servers check out a project’s source code from the central repository; compile, measure, and test it; then e-mail the results to a central database server and Web display.”¹

Testing with this kind of system is much more thorough than can be accomplished by any manual approach. In addition to testing code across several platforms, a variety of compilers and compiler diagnostic settings can be used. The end result is that compilation-specific bugs are avoided as well as code that is incompatible with certain development tools.

In Vanu’s case, implementing SDR entirely in software makes a continuous automated test system particularly effective. The role played by special-purpose hardware is much larger in portable SDR implementations, and the test challenges are different. For example, algorithms executing within a specific type of FPGA or DSP do not need to be ported to many other types of devices in the way that Vanu software is ported to many platforms.

Facilitating Portable SDR

The hardware emphasis in portable radio applications is largely a consequence of power, size, and cost restrictions. The flexibility of a programmable SDR approach is desirable but has been compromised in the past by lack of suitable components.

The Sandblaster^® SB3000 DSP Series developed by Sandbridge Technologies is a special-purpose communications platform that can be programmed in C and dynamically reconfigured in nanoseconds. The device has been designed for parallel, real-time communications system processing. Low power consumption has been achieved by design optimization. The instruction set supports simplified decoding for vector and compound operations as well as sleep, nap, and doze reduced-power modes. Multithreading optimizes efficiency by turning off threads and allowing the use of slower latency memories. Finally, the circuitry runs at 0.9 V, and its organization minimizes the number of areas that are active at any time.

The Sandblaster SB3011 SOC was included in a paper presented at the SDR Forum Technical Conference 2006.² In addition, a much more comprehensive discussion of the SB3000 device and its programming environment is available in a separate paper on the company’s website.³

Sandbridge Technologies has focused on baseband processing, leaving the RF front end and digitization to others. These areas are not trivial, largely because of power limitations and the range of protocols to be covered, each with its own mix of noise figure, bandwidth, sampling rate, and precision requirements.

The Sandblaster DSP
DSP technology provides several benefits. Fast signal-processing computations require the multiply-accumulate units that DSPs typically provide, and historically, DSPs have supported real-time parallel execution. But they aren’t programmed in a high-level language. The new architecture combines DSP performance with the advantages of high-level programming.

The current SB3000 features a 64-b compound instruction set in which specific 21-b fields may issue multiple suboperations including data parallel vector operations. Each instruction is completely interlocked and defined so that it has no visible pipeline effects. This means that fast interrupt response is possible.

Four instances of the Sandblaster core are provided in the SB3000 along with an ARM microcontroller that functions as an applications processor. In addition, the chip contains numerous digital interfaces. Connectivity to external systems is via the USB port, and RF and front-end chips are controlled from the JTAG, SPI, and I²C buses (Figure 2).

Chip performance is reported to be equivalent to greater than 12 Gigabit Ethernet media access controls (GMACs) at a maximum 800-MHz clock speed. Internally, the microarchitecture uses token triggered multithreading to allow memory access at a slower rate and in a predetermined order. The chip supports 2-Mb/s WCDMA 3G transmission in real time and separately can execute the digital baseband processing for GPRS, 802.11b, Bluetooth, or GPS.

The latest SOC in the series, the SB3500, currently is under development using an enhanced instruction set and extended Sandblaster 2.0 architecture. Chip performance is expected to be 30 GMACs peak. The SB3500 will support systems up to long-term evolution (LTE) at 50 Mb/s and separately, broadband multiple-input multiple-output-orthogonal frequency division multiplexing (MIMO-OFDM) systems such as 802.11n and 802.16e including multimedia standards H264 and MPEG4. The new chip is expected to be available in Q3 2008.

On the software side, Sandbridge has developed a vectorizing compiler as well as a simulator based on the same techniques. The benefit of such a compiler is in bridging the gap between what a group of C statements means and how that can best be implemented on the target DSP platform.

In the past, this difficult compiler problem was approached in a variety of ways. Early DSP architectures were designed for fast operation but not necessarily with compilability in mind. Architectures with very long instruction words (VLIW) improved instruction orthogonality, which helped the compiler problem but greatly expanded program size.

Libraries of functions coded in assembly language also can be used to overcome DSP programming problems. Control code can be written in C and the dense signal processing algorithms called from a library. Of course, somebody has to write and test the library functions, but if they are used often, this can be a viable approach.

Finally, you could use intrinsic functions. In this method, the compiler writer provides a list of low-level instructions equivalent to what looks like a C code function call. During preprocessing, the C function is replaced by the list of low-level DSP instructions. This works but has shifted what was an assembly language programming job to the compiler writer.

Instead of these techniques, Sandbridge has used modern supercomputer semantic analysis. The compiler ana- lyzes the C code, automatically extracts the DSP operations, and generates optimized multithreaded DSP code. This process can be very complicated. For example, such a compiler may have to significantly reorder loops coded in C either by splitting or jamming them together depending on the nesting depth.

The Sandbridge integrated development environment (IDE) is based on the open source Netbeans IDE and is the GUI to the C compiler, assembler, simulator, and debugger. Within the IDE, you can create, edit, build, execute, and debug an application. Access to multithreading is via either Java threads or portable operating system interface (POSIX) pthreads.

A Programmable Front-End IC
To address the RF front end, BitWave Semiconductor has developed the Softransceiver™ RFIC which features dynamically reconfigurable functional blocks (Figure 3). The device provides the full transmit and receive front-end chains. Transmit covers the baseband interface to the driver amplifier, and receive includes the low-noise amplifier (LNA) back to the baseband interface. The required ADC, DAC, filters, synthesizers, and DSP are integrated in the RFIC together with test and calibration circuitry using 130-nm digital CMOS technology.

Based on the performance profiles of several popular wireless protocols, the company’s designers created a flexible architecture that can be programmed to suit the application. For example, the on-chip narrowband low-noise amplifier is tunable over a wide frequency range to cover GSM 900, UMTS, and 802.11g requirements.

Throughout the design, the emphasis has been to balance performance, power, and cost. This results in a small, low-power IC that addresses the need for multiprotocol communications systems.

The RF tuning range extends from 700 MHz to 3,800 MHz, and bandwidths from 25 kHz to 20 MHz are supported. Virtually all popular mobile standards within this range are available including:
• UMTS (GSM, GPRS, EDGE,  W-CDMA, HSDPA)
• CDMA2K (IS-95B, 1xRTT, EV-DO)
• 802.11b/g, WiMAX, WiBro
• iDEN, AMPS, PHS, IS-136
• DVB-h, DVB-T, DTV, ISDB-T, DAB
• Bluetooth, GPS

Each of the on-chip functional blocks is controlled by a separate register. So, at a basic level, you tune the chip characteristics for a given protocol by suitably programming the bits in those registers. A chip statically configured in this way will operate in compliance with the selected standard.

However, depending on many factors that could affect operation, such as temperature, power supply voltage, local RF noise, and receive signal power level, the performance may not be optimum. An on-board 8051-style microcontroller is available to monitor performance and make corrections using closed-loop feedback.

A crystal-controlled clock oscillator provides an accurate time and frequency reference, and a precision resistor together with an accurate integrated current source support current, voltage, and power measurements. Given that all the relevant parts of an RF measurement system are already implemented and separately controllable in the RFIC, the opportunity for a sophisticated self-test capability exists.

Benefits

For a number of years, cell phones have embedded a microprocessor, typically an ARM core, to handle much of the baseband processing and control. If performance in either of these areas was inadequate under some conditions or if updates to related features were required, it involved a software change. New models could be based on the same platform if the hardware could handle higher speeds and whatever other changes might be needed. Much of the time, designers didn’t have to develop a completely new platform.

The same types of advantages are associated with the Sandbridge and BitWave ICs. These general-purpose platforms address baseband and RF front-end signal processing, respectively. In the same way that an ARM core can be reprogrammed to handle new requirements, so too can developers reprogram these ICs without needing to alter the hardware design. This means that the time and effort associated with handling a new communications protocol are much reduced.

Sandbridge listed six benefits:
• Reconfigurable solutions are more flexible, allowing multiple communications protocols to dynamically execute on the same transistors to reduce hardware costs. Specific functions such as filters, modulation schemes, and encoders/decoders can be reconfigured adaptively at run time.
• Several communications protocols can be efficiently stored in memory and coexist or execute concurrently. This significantly reduces the cost of the system for both the end user and the service provider.
• Remotely configurable protocols provide simple and inexpensive software version control and feature upgrades. This allows service providers to differentiate products after deployment.
• The development time of new and existing communications protocols is significantly reduced, providing an accelerated time to market. Development cycles are not limited by long and laborious hardware design cycles. With SDR, new protocols are quickly added as soon as the software is ready for deployment.
• SDR provides an attractive method of dealing with new standards releases while assuring backward compatibility with existing standards.
• Any defects found in the field can be fixed by changing the software, possibly even transparently to the user, without requiring a hardware change or chip respin.

BitWave listed additional benefits:
• With SDR-enabled portable devices, consumers could buy a phone first and activate it on the network of choice or could benefit through post-sale service activation.
• Mobile virtual network operators could partner with multiple networks to obtain the best business value unrestricted by the constraints of any particular protocol or frequency.
• Device OEMs can realize supply-chain improvements with substantial inventory reductions because of the development of standard radio modules and platforms.

Possible benefits extend beyond these to include continuous self-health monitoring. It is feasible for a device to determine its own degree of impairment and report it to the user. A radio could even repair itself or upgrade its own operation.

With a comprehensive self-test capability, if a radio has once been proven to comply with one or more protocols, it should be possible to continuously confirm compliance. Further, similar to the error codes provided by your car’s engine control unit, the Sandbridge and BitWave devices have sufficient intelligence to minimize troubleshooting should it be necessary.

Summary

Although there are obvious commercial advantages to many of the nine points listed, BitWave stated the situation clearly: “Commercial application of these new architectures will depend on the ‘business value’ they provide. Once deployed into a network and as the carrier requirements for multimode devices become more demanding, the value that these new architectures offer throughout the value chain will steadily increase.”⁴

It’s easy to focus on the technical innovation that underpins new SDR products, but the real reason they will succeed is that they satisfy commercial power, performance, and cost requirements. Of the three companies, Sandbridge, BitWave, and Vanu, only Vanu has publicly announced a few customer applications.

One of these was a demonstration of a 700-MHz prototype Femtocell that combined Vanu’s Anywave SDR technology and BitWave’s Softransceiver RFIC. Another announcement described how Mid-Tex Cellular, a rural central Texas cellular operator, is using the Anywave infrastructure to simultaneously provide CDMA and GSM service.

However, given the interest BitWave and Sandbridge also have generated in the industry, actual SDR implementations using the companies’ products are expected soon.

References

1.Nimmer, J., et al., “Continuous Automated Testing of SDR Software,” Vanu, 2006.
2.Raja, T. and Glossner, J., “Trends in Low Power Handset Software Defined Radios,” Sandbridge Technologies, 2006.
3.Glossner, J., et al., “The Sandbridge Sandblaster^® Convergence Platform,” Sandbridge Technologies.
4.Org, E., et al., “Software Defined Radio Architectures for Mobile Commercial Applications,” BitWave Semiconductor.

June 2008