Boundary scan is well established in the industry, a fact strengthened by major ATE companies like Agilent Technologies and Teradyne that have added boundary scan capabilities to their in-circuit testers. The next step is to increase its application by combining it with multiple test technologies and improving its features such as ease-of-use in design validation, repair on the manufacturing floor and in field service, and fault injection for non-boundary scan devices.
Today, boards are populated with both boundary scan and non-boundary scan devices. Boundary scan coverage is easy. All boundary scan software has the capability to determine how much coverage the board under test has. It even can determine pin coverage as well as net coverage. But how much coverage do we have on a non-boundary scan device?
Different software programs use alternative methods to test a non-boundary scan device. It usually is called cluster testing. These non-boundary scan devices can be line drivers or buffers with or without inversion, rerouting devices such as multiplexers, or more complex devices such as memories and FIFOs.
Boundary scan test software usually has its own models for memories or FIFOs that you can modify according to your needs and generate a test. But to successfully test non-boundary scan devices, you must write your own patterns according to the device data sheet and board topology.
And, how effective are these patterns? Is it enough simply to pass the test? Two case studies delve into this issue.
Case One: A Simple Octal Bus Switch
A simple octal bus switch, the 4CBT3245, is the focus of case one. Figure 1 shows a quick cluster test pattern for this device.
A first look at the pattern indicates all the pins are toggling properly, and that is what we are looking for. The purpose of a structural test such as ICT, JTAG, and flying probe is to catch manufacturing faults, not to check device functionality. The manufacturing faults are those that occur during the manufacturing process and include unwanted shorts and opens on the board under test or wrong, misoriented, or missing components. So if a pin can toggle high or low, it is OK.
But OE is always low, which means the device is always enabled. What if it is stuck at low on a DUT? With this template we cannot test the OE pin for a stuck-at low fault unless we modify it to detect stuck-at low on OE. That means this template does not have 100% coverage.
Even after modifying the template, it cannot detect a short on even or odd inputs or outputs because they are toggling high or low at the same time. A more appropriate template would be a walking zero/one template.
Case 2: 1-of-8 Decoder/Demultiplexer
A test template for the SN74LS138 Decoder/Demultiplexer is shown in Figure 2. All the pins are toggling properly in the template. But according to Table 1, there is no stuck-at low coverage on E1 and E2 pins nor for a stuck-at high on E3 pin.
Fault Injection Technique
To evaluate the quality of our cluster templates, we need a fault injection tool, which always has been available in in-circuit testers. The fault injection method evaluates a template for any stuck-at faults as well as test quality by examining pin fault coverage and state fault coverage.
Fault injection is intended to be used after a test has been debugged and is passing. It also evaluates the quality of the test by examining the capability of the template to detect different faults, generates a detailed report of each pin with the type of coverage it has, and calculates total pin coverage. A typical report for the second case study is shown in Table 2.
Fault Injection Algorithm
Usually, board test engineers are interested in pin fault coverage. There are three types of pins on a digital component: input (stimulus), output (measure), and input/output (stimulus/measure). To assess the pin fault coverage of a component, one of the following tests must be run for each pin depending on pin type:
• For input pins, fault injection should simulate stuck-at conditions for each pin. The test pattern being evaluated must detect a stuck-at low and a stuck-at high to have pin fault coverage.
• For each output pin, the test pattern must expect both a high state and a low state before it can be declared to have pin fault coverage.
• For input/output pins, the pin is considered to have pin fault coverage if the test can detect both an input stuck-at low state and an input stuck-at high state or an output stuck-at low and an output stuck-at high.
Conclusion
To reach its maximum potential, boundary scan test requires new tools and techniques. Fault injection can be useful in evaluating the quality of a cluster test template and in calculating actual test coverage for every non-boundary scan device tested with boundary scan techniques.
About the Author
Vaheh Satourian is a senior test engineer at Artaflex where he prepares and maintains boundary scan and in-circuit tests and performs testability reviews and DFT reports. He began his career as a test engineer in 1999 at Acculogic. Mr. Satourian received a B.S.E.E. from Guilan University in Iran. Artaflex, 215 Konrad Cres., Markham, ON, L3R 8T9, Canada, 905-479-9777 ext. 283,
e-mail: [email protected]
November 2008