Resolving Test Challenges for High-Speed Interfaces

High-speed interfaces for the computer, consumer, and communications markets have moved dramatically forward, increasing from a few hundred megabits per second to much faster gigabit speeds, in some cases up to 10 and 12 Gb/s. These rapid improvements in performance have created significant test challenges, requiring major changes in test methodologies and, in many cases, true cross-domain test approaches.

A quick review of the improvements in major standard interfaces illustrates the pace of change:
•?Ethernet now supports 10 Gb/s on its way to 40 Gb/s and 100 Gb/s. The PCI Express computer bus is moving from 2.5 Gb/s to 5 Gb/s with a short-term roadmap to 8 Gb/s and 10 Gb/s.
•?The SATA bus is going from 1.5 Gb/s to 3 Gb/s with a roadmap to 6 Gb/s. Other network interfaces such as XAUI already are at 10 Gb/s and moving to 12 Gb/s with 25 Gb/s on the
horizon.
•?The S3200 FireWire interface for multimedia transport also is moving toward 3.2 Gb/s from its current 800-Mb/s speed; the newer HDMI multimedia interface is moving from its current multichannel 1.65 Gb/s to 3.3 Gb/s. And USB is headed toward 4.9-Gb/s speeds.
•?Memory interface speeds also are increasing. DDR architectures currently are running at 800 Mb/s and quickly moving to 1.6 Gb/s and 2.4 Gb/s, then on to 3.2 Gb/s and 6.4 Gb/s, and further out to 8 Gb/s and 16 Gb/s.

Figure 1. Multiple Sine Wave Frequencies Sum to Make Up a Digital Waveform

To guarantee measurement quality of DUT transmit and receive signals, test instrumentation and the interface connection should have a bandwidth equivalent to the third harmonic of the highest frequency of interest and, in some instances, the fifth harmonic. For a 10-Gb/s signal, the highest code frequency is a mark space clock-type pattern, which at 10 Gb/s represents a 5-GHz cycle/period bandwidth. However, a digital signal is composed of many frequency components where the true level of speed is the edge-rise and fall-time frequencies (Figure 1). As a result, the maximum bandwidth is determined by these rise and fall times and not the base period bandwidth.

At 10 Gb/s, the rise and fall times can be as low as 20 ps. To convert this rise and fall time into its -3 dB equivalent bandwidth, use the well-known equation

BW = 0.34/rise time

At 20 ps, this would indicate a fundamental -3 dB frequency of 17.5 GHz and a third harmonic bandwidth of 52.5 GHz and not the 15 GHz associated with a 5-GHz sine wave equivalent.

A bandwidth of less than the 52 GHz will tend to filter and roll off the device’s signal edges. This results in a reduced rate of change of the rising and falling edges, a condition that converts more of the device’s random noise into jitter at the transition points and effectively closes down the signal eye’s waveform tolerance (Figures 2 and 3). Consequently, good devices could potentially fail, reducing yield, revenue, and profit.

Figure 2. High Bandwidth Channel
Courtesy of Bertscope
Figure 3. Restricted Bandwidth Channel
Courtesy of Bertscope

Custom-Tailoring the High-Performance Test System

High-performance test systems are custom tailored to the device via what is known as a loadboard or interface board. The board houses interface conditioning and buffering circuitry between the DUT and test instrumentation, and it includes the most critical circuitry for maintaining measurement accuracy.

Another critical link is the test contactor, the interface between the device being tested and the loadboard. Under ideal test conditions, the DUT is electrically soldered directly onto the loadboard. But this is impractical in a test environment where many devices have to be tested and, in many cases, in just a few hundred milliseconds. In this case, a contactor has to be used.

The contactor has to deal with the electrical characteristics of all the different interface connections required and with the mechanical abuse of thousands of device packages being inserted and removed by an automated handling system. Designing a contactor that can achieve all these requirements is a challenge in itself.

There are two main users involved with test contactor selection:
•?The test engineer or product engineer who is primarily interested in establishing the ultimate electrical performance of the semiconductor device. He or she is looking to accurately verify the electrical specifications to establish the highest selling price for the product.
•?The production engineer who monitors electrical performance specified by the product engineer in a production environment where mechanical consistency, reliability, dependability, and the lowest cost over a large number of device insertions are the prime concerns. These measurements also must be performed in an automated handling environment that can be mechanically very harsh on any device interface.

Electrical Challenges

The test contactor has to meet many different electrical specifications at both DC and high frequencies. These parameters include overall electrical length, contact resistance, inductance, and capacitance, all of which affect operating bandwidth. For high-frequency applications, the contactor becomes part of an overall transmission line, so S-parameters for insertion and return loss must be considered. Crosstalk between contacts also must be addressed. However, many packages surround high-frequency pins with ground pins that help isolate and reduce crosstalk interference.

At lower frequencies and in power management applications such as low-drop-out (LDO) regulators and power output stages, contact resistance and inductance can distort the very low voltage specifications required. The objective here is to minimize the electrical contact length and provide the lowest series resistance material possible.

Kelvin connections also help compensate for voltage drop across a contact and offset resistance variations based on debris buildup on the contact surface. As the contactor has both inductance and capacitive elements, these can combine in feedback networks and create oscillation and noise conditions within the circuit. Minimizing these components is a distinct advantage.

Mechanical Challenges

Contactor selection also involves all the mechanical issues associated with device presentation and alignment. There are a number of semiconductor interconnect pitch and profile dimension tolerances, package tolerances, and handling-systems alignment and presentation tolerances. All these tolerances must be accounted for in the overall contactor housing design. Many of the tolerances are specified in thousandths of an inch or in millionths of a meter, and all these tolerances interact with each other in multiple combinations.

To overcome these obstacles, a contactor must provide consistent and repeatable electrical performance over a large number of device insertions and accommodate multiple mechanical variances. This only can be achieved by a contactor that uses highly accurate and adaptive design parameters.

Lead-Free Package Interconnects

The introduction of lead-free package interconnects has challenged both electrical and mechanical aspects of contactor technology by reducing throughput efficiency and increasing the cost of test.

The most common lead-free interconnects are Matte tin, nickel-palladium-gold (NiPdAu), and tin-silver-copper (SnAgCu). All come with surface oxides that have to be penetrated to achieve a good electrical connection. Although NiPdAu and SnAgCu are harder than the oxide-rich Matte tin, they all cause increased and highly variable contact resistance based on residual oxide debris.

In a dynamic application, such as production testing, the primary issues are breaking or wiping through these tin oxides to form a good low-resistance connection and preventing oxide buildup on the contact surface. Other mechanical factors that affect overall interconnect electrical performance include contactor contact plating, device ball alloy amalgamation, effective electrical contact surface area, and the overall mechanical force required to achieve and maintain acceptable electrical performance.

Penetration and self-cleaning mechanical action are essential to minimize the effects of device interconnect surface oxides, test contactor contact oxide buildup, and amalgamation between the contactor contact and the device ball material. Once oxide penetration has been achieved, intersurface asperity deformation has to be modeled and analyzed. This establishes the true contact surface area, contact resistance, and current-carrying capacity.

Finally, the mechanical force objectives are to apply the right amount of force when working in conjunction with the other contact pin dynamics and provide a true contact surface area necessary to generate repeatable low-resistance connections on all contacts and for all devices tested.

Semiconductor Package Roadmap Considerations

The International Technology Roadmap for Semiconductors (ITRS) consistently forecasts increases in speed, miniaturization, and integration of high-performance functions into semiconductors and their associated packages. As these package and pitch dimensions continue to shrink and contact I/O counts rise, miniaturization of the socket interface creates its own set of challenges.

For high-frequency applications, the JEDEC packaging coplanarity specification tolerances are very wide and affect the compliance requirements of high-frequency test contactors. Fortunately, packaging vendors maintain much lower tolerance specifications than those specified by JEDEC, allowing test socket compliance and consequently electrical length to be reduced and bandwidth increased.

These more demanding high-frequency applications are an area where traditional spring-pin socket solutions now are experiencing some serious limitations, both electrically and mechanically. And the number of alternative solutions that have emerged, which claim to provide a higher level of electrical performance over their spring-pin cousins, has other electrical and mechanical limitations. They also exhibit a less-than-optimal economic model in a production environment.

Contactor Value

Any new solution must provide the necessary electrical performance required to sustain the value economics in a production environment. Value in this case is improving test throughput and cost efficiency for high-performance lead-free devices, which are dependent on three major factors: test cell availability, test throughput, and first-pass yield quality.

Test cell availability is when the cell is testing parts. Test cell changeover and setup and contact cleaning and rebuilding render the cell down and unavailable. Contactors that require less frequent cleaning or replacement, and which can be set up, cleaned, and rebuilt in a very short time, add to test cell productivity and availability. Contactors with self-cleaning features reduce the cleaning cycle and delay amalgamation effects. Contactors that can be easily rebuilt reduce rebuild errors and downtime or the need for expensive, hard-to-correlate duplicate loadboard hardware while the contactor is being serviced.

Test throughput is represented by the number of units tested per hour via an optimized test program and minimized handling time. Both test-program wait states for electrical and mechanical settling and guard band extensions to accommodate electrical variances in the interface impact overall test productivity.

Yield quality is a measure of first-time yield success and its true throughput value. The need to retest parts based on inconsistent contact continuity reduces throughput and yield expectancy. Contactors with short cleaning and rebuild cycles favorably impact first-time yield, downtime, and cost.

About the Author

Paul F. Scrivens is a senior product manager at Johnstech International. Mr. Scrivens has spent the past 25 years in the semiconductor test industry, specializing in the area of mixed-signal design and test where he held a number of senior business and marketing positions. Before joining the ATE industry, he was a mixed-signal system and circuit design engineer based in the United Kingdom. Johnstech, 2450 Scott Blvd., Suite 305, Santa Clara, CA 95050, 408-448-2020, e-mail: [email protected]

July 2009

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