Optimizing Maintenance For Turbine Engines

For years, the defense and military communities have been faced with increasing pressure to incorporate advanced Prognostic Health Management (PHM) solutions into high-value turbine jet engines. Beginning around 1994 and coinciding with the launch of the Joint Strike Fighter program, interest in PHM development has escalated rapidly within the U.S. Navy and U.S. Air Force as a targeted, critical technology for improving the affordability of advanced aircraft systems through reduced maintenance costs and improved useful-life survivability.

In theory, PHM systems are designed to detect engine faults and predict remaining useful life with a low probability of error. This is accomplished by implementing PHM decision-making algorithms on high-speed data acquisition and processing platforms.

These algorithms combine a number of technologies, including signal-processing methods, physics-based probability failure models, empirical data-driven models, and high-level reasoning intelligence, to consolidate the gathered information. Put simply, PHM aims to eliminate surprises in the operation and maintenance of turbine engines through advanced, real-time diagnostics and monitoring.

Today, however, PHM technology is at a crossroads. While some commercial OEMs and academic and private entities have made substantial progress in developing a variety of capable algorithm concepts, the missing piece to broad military and commercial acceptance has been processor hardware of sufficient strength and resiliency that can be embedded on the actual aircraft in or near the turbine engine itself.

In response to this need, the U.S. Air Force turned to DSPCon, as represented by its recent award of a Phase II Small Business Innovation Research (SBIR) Grant, to continue development of an optimized hardware solution. The goal is to implement PHM systems with a high degree of certainty through the use of a high-performance processing platform that has size, weight, and power (SWaP) consumption characteristics favorable for embedding the system into an aircraft.

When fully developed, the company’s solution will have sufficient processing power to apply sophisticated, numerically intensive PHM algorithms in real time. It will be able to archive the processed and raw sensor data from a wide variety of engine monitoring sensors. Also, the solution provides communications capabilities with the aircraft engine controls systems currently aboard the aircraft.

The solution will represent an improved computational capability over existing Full Authority Digital Engine Control (FADEC) hardware and software systems through the use of optimized signal-processing algorithms and a robust, small form-factor processor technology code-named BFX. This improved capability will facilitate more thorough, rapid detection and analysis of equipment degradation so appropriate maintenance can be undertaken before the developing problem evolves into an equipment failure. The technology will target commercial and advanced aircraft applications.

Limitations of Current FADEC Systems

FADEC systems installed in the vast majority of today’s commercial jet aircraft use hardware platforms based on older processor technologies. While sufficient for simple, short-term data capture, routine diagnostics, and alarm monitoring, the chipset does not exhibit the sufficient amount of processing power required to host complex, advanced PHM algorithms and related real-time data acquisition, analysis, and archiving for historical comparison of events and intelligent alarm notification.

The DSPCon solution will serve as an adjunct, not a replacement, for currently deployed FADEC systems. It will feature a new function-specific board design with significant SWaP benefits over today’s commercially available board designs and an increase in processing speed.

Current IC design approaches used throughout the electronics industry focus on putting many functions on large cards, such as single board computers in which processors, programmed logic, I/O, and archiving functions are assembled on a single board. This approach is a continuation of past trends to place many functions on a single board due to the need for reliable, high-bandwidth communications between the individual electronic components.

In newer designs, these functions are almost completely connected using gigabit links such as PCI Express. While still satisfactory for a number of current applications, in general, these boards have more functions than most users require. In addition, up to 50% of the board may not be used for a given application, which, in many cases, increases the power requirements for any integrated system. As such, this limits the designer’s ability to shrink the footprint of the system and complicates heat-removal issues.

Additionally, COTS hardware is still widely used to integrate many applications that require low-volume and high-mix hardware configurations such as ruggedized military applications using conduction-cooled boards in VME, cPCI, and REDI form factors. While this has been an adequate solution for vehicles with a lot of space to house a system, it is unacceptable for the highly confined real-estate landscapes of today’s military and commercial jet engines.

For many current SWaP-optimized applications, the prevalent design approach in the industry remains based on the 3U VPX and 3U Compact PCI standards in spite of inherent physical limitations. An alternative approach in processor technology represents a significant improvement in space and power requirements along with an improved economic profile over time. This is the essence of the BFX approach.

The BFX is a modular design concept composed of function-specific electronic boards, as opposed to single-board computers, which allows for a smaller footprint. The individual boards are interconnected by a high-speed serial I/O fabric with a bandwidth of greater than 5 GHz.

Its modularity accommodates expansion in both processing and archiving capacity through additional processor or memory boards. It also supports the integration of newer processor designs by requiring them to be mounted on electronic boards that meet the I/O requirements of the DSPCon architecture.

Figure 1 illustrates the PHM processor design as a group of modular, function-specific boards including a data-processing module, a solid-state memory archiver module, sensor-specific I/O modules, and a FADEC interface module. The small-footprint design is rugged and lightweight. Due to the use of low-power consumption components, the heat dissipation is more easily managed, making the design suitable for embedding in an aircraft.

Figure 1. PHM Processor Platform Hardware

The fully functional PHM processor platform shown in Figure 1 is housed in a chassis that has a 4″ x 4″ x 3″ footprint, weighs approximately 4 lb, features conduction cooling, and consumes approximately 45 W of power. Additional processing or archiving capability and sensor inputs require more boards and a larger chassis.

The low-power consumption of the PHM processor platform is achieved through the use of a chipset requiring little power, such as the Intel ATOM processor. While there are many alternative high-speed processors developed more specifically for the video gaming industry, all consume from 150 W to 250 W of power.

We have determined that the ATOM processor has sufficient processing capability for the PHM platform yet only consumes on the order of 2.5 W. This considerably alleviates the power-dissipation management issue. The design approach is flexible enough to allow for processors other than the ATOM to be used should the requirements of the system demand it.

Engineers at the company already have successfully tested and used this approach in several data acquisition systems including a high data rate signal intelligence recorder for the U.S. government and a system for processing hyper-spectral camera images in real time aboard a small tactical, unmanned aerial system. The latter design was carried out under another Phase II SBIR.

A Closer Look at the BFX Design Concept

Our approach to implementing the modular SWaP-optimized design of the PHM processor platform on a commercial level is predicated on the use of rugged, compact boards sharing a common footprint and a serial I/O structure for all of its electronic boards, regardless of their individual functions (Figure 2). It allows the processor card, for example, to be replaced without changing the overall architecture once the bus interface is designed. This design paradigm also accommodates easy board replacement as opposed to currently available technologies that require a complete system changeover when one single-board component fails.

Figure 2. Comparison of Footprints for BFX and VPX Standards

The compact, modular PHM platform houses all the processors, sensor interfaces, and the archiving and FADEC I/O functions that comprise a complete, self-contained PHM unit that can withstand the environmental stress imposed by a turbine engine. The ATOM processor, which represents the heart of clinical diagnostic capabilities within the PHM platform, may be augmented by a scalable Xilinx preprocessor that can add processing power for highly parallel functions such as FFT.

The sensor I/O modules interface with a gamut of sensor types typically used in engine monitoring, diagnostics, and alarm notification. The sensor I/O components combine integrated signal-conditioning functionality and high-speed ADCs to provide the data acquisition requirement necessary to capture all critical data within the PHM scope of operation.

An improved solid-state memory module contains sufficient capacity to record crucial events as well as the timing sequence of these events to monitor and characterize data sets related to the development and progress of ongoing engine faults. This architecture facilitates expanding PHM knowledge bases so faults can be predicted and recorded reliably and as early as possible.

The BFX design paradigm also allows for an interface module that communicates with commercially deployed FADEC systems. This module can operate in two ways. If desired, the FADEC interface can receive information directly from the FADEC to enhance PHM decision-making within the engine. Additionally, the FADEC can poll the results of PHM to enhance its own functionality set, resulting in improved overall engine performance and safety.

The complete BFX board assembly will handle a variety of algorithms that are of interest to the PHM community, readily advancing its acceptance into the mainstream of maintenance practices within the military and commercial aerospace industry.

About the Authors

Mitchell Wlodawski is DSPCon’s chief scientist. He has extensive experience in fiber optics, digital signal processing, and optical sensor technology and has developed numerous algorithms and physics-based models for a variety of commercial and government programs. Mr. Wlodawski received an M.S. in electrical engineering from Columbia University. e-mail: [email protected]

Bill Pankracij is the marketing communications and PR manager at DSPCon. He has more than 20 years of public/investor relations and marketing experience in the software, telecommunications, and semiconductor industries. Previously, Mr. Pankracij held management positions at several technology start-ups as well as at North American Philips, Perkin-Elmer, and BellSouth. e-mail: [email protected]

DSPCon, 380 Foothill Rd., Bridgewater, NJ 08807, 908-722-5656

January 2010

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