Virtex-7 uses 2.5-D technology to deliver 6.8 billion transistors

Xilinx Inc. has announced first shipments of its Virtex-7 2000T FPGA, which incorporates 6.8 billion transistors to provide customers access to 2 million logic cells. Xilinx says that's equivalent to 20 million ASIC gates. The new devices can serve as ASIC replacements and in ASIC prototyping and emulation applications.

A Virtex-7 2000T FPGA can accommodate designs that would be impractical to implement using multiple FPGAs. In a Xilinx white paper, Kirk Saban notes that I/O limitations can inhibit the successful partition of a design across multiple FPGAs. The package I/O limitations often impose performance-limiting data-buffering requirements, and even at the die level, I/O resources don't scale with internal core logic resources. Time-domain multiplexing can increase virtual pin count, but it imposes latency and power penalties.

The devices employ what Xilinx calls Stacked Silicon Interconnect (SSI) technology, which avoids the problems of driving hundreds of package-to-package signals across printed-circuit-board traces. With SSI technology, each device is fabricated from multiple 28-nm silicon dice, mounted on a passive silicon interposer. The interposer contains high-bandwidth, low-latency die-to-die connections that connect to each die using microbumps. Connections to the package substrate occur by means of through-silicon vias (TSVs) and controlled-collapse chip connection (C4) bumps.

The interposer itself is built on what Xilinx in the white paper calls “a low-risk, high-yield” 65-nm process; it provides four layers of metallization and can accommodate tens of thousands of traces. Xilinx says its SSI technology provides multi-terabit-per-second die-to-die bandwidth through more than 10,000 device-scale connections.

See a diagram of an SSI device here.

EE-Evaluation Engineering will be following the test challenges posed by stacked-die technologies throughout 2012. We welcome your input. Post a comment or e-mail me.

Posted 10/25/2011 2:30:31 PM. View all posts.

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