IBM said to employ ASML EUV tool for 7-nm chips

July 9, 2015

IBM is reportedly employing an ASML prototype extreme ultraviolet lithography tool to develop 7-nm test chips at SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering, according to Don Clark at the Wall Street Journal. Commercial 7-nm chips are unlikely to be available for several years. Clark quotes Dan Hutcheson of VLSI research as saying, “It’s a big challenge for the industry to get from here to manufacturing.”

Clark notes that an EUV tool can cost $150 million, vs. about $50 million for a 193-nm tool, and EUV tools now are comparatively slow. However, Clark quotes Michael Liehr, executive vice president for innovation and technology at the SUNY Poly research center, as predicting that ASML would boost the output of its EUV tools over the next four to six years.

IBM announced in January that more than 220 engineers and scientists who lead IBM’s advanced chip research and development efforts at SUNY Poly Albany Nanotech campus would become part of IBM Research. “The groundbreaking work that these engineers will conduct at SUNY Polytechnic Institute reflects IBM’s long-term commitment to inventing the future of microelectronics,” said Dr. John Kelly, senior vice president of research at IBM, in a press release. “The IBMers working at SUNY Poly possess unique skills and capabilities, positioning our company to drive development of the next generation of chips and to fuel a new era of computing.” IBM said it had invested $3 billion in the effort to shrink transistors to 7 nm and beyond.

Meanwhile, Clark reports that Intel, which has invested $4 billion in ASML, contends it can make 7-nm chips profitably without shifting to EUV. Nevertheless, he adds, ASML announced in April the sale of 15 EUV tools to an unidentified U.S. customer—widely believed to be Intel.

Update: IBM confirms fabrication of a SiGe 7-nm test chip.

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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