Synopsys touts test technology at ITC

Oct. 12, 2015

Anaheim, CA. Synopsys chose the International Test Conference held here October 6-8 to highlight three advances in test technology. Robert Ruiz, senior staff marketing manager, said the company had developed new ATPG technology that runs ten times faster while requiring 25% fewer patterns. He added that Synopsys test tools have achieved certification to ISO 26262 for automotive applications. In addition, he outlined highly accurate defect modeling and testing for FinFETs and emerging nodes.

Ruiz also summarized several presentations from the Synopsys User Group meeting held in conjunction with ITC. Avago described using advanced fault models to achieve < 10 DPPM, Realtek employed pin-limited compression to achieve 4X to 13X TATR for pin-limited ICs, STMicroelectronics described the implementation of in-system power-on self-test, and Teradyne commented on employing hierarchical test to save weeks of debug.

With regard to the new ATPG technology (see related article here), Ruiz said a growing number of tests are leading to longer test times and longer ATPG run times, but shrinking schedules require faster ATPG. At the same time, compute cores per machine are increasing, but, he added, core usage for ATPG is constrained by memory.

The new technology, he said, is fine-grained and employs memory-efficient multithreading, eliminating the memory bottleneck and speeding ATPG as cores are added.

In addition to speeding pattern generation, Ruiz said the new technology also leads to 10X faster diagnostics through intelligently partitioned areas of interest (“relevant logic cones”). The resulting analyze, partition, and parallelize operations provide faster reports of defect locations while using less memory. In addition, new algorithmic advances enable a higher number of defects that can be detected with each pattern—thereby offering pattern reduction of typically 25%, Ruiz said, and reducing time on the tester and test costs.

With regard to ISO 26262 certification (see related article here), Ruiz said the IC content in automobiles is growing at > 6% per year, forecast to reach $570 per vehicle in 2017, according to IC Insights Market Drivers Report. Parts in safety-critical circuits must meet strict requirements such as those defined in ISO 26262. Ruiz said that TetraMAX ATPG, DesignWare STAR Memory System, and STAR Hierarchical System have all been certified by SGA-TÜV for use on automotive circuits, including the most safety-critical (ASIL D). This certification, he said, reduces the time and cost for Synopsys customers to obtain safety qualification for their design processes and tools.

Ruiz concluded by describing cell-aware tests for FinFETs and emerging nodes. New fault models are required for new process defects, he said, with cell-aware faults based on transistor-level defects inside cells. The faults, he said, are correlated with defects observed in silicon; the models are useful for early yield ramp and high-quality testing to detect prominent defects. He added that Synopsys using the Liberty library for accurate timing and is collaborating with foundries and semiconductor companies to correlate effectiveness on silicon parts.

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