Washington, DC. At this week’s IEEE IEDM conference, nanoelectronics research center imec demonstrated record enhancement of novel InGaAs gate-all-around (GAA) channel devices integrated on 300-mm silicon and said it is exploring emerging tunnel devices based on optimization of the same III-V compound semiconductor.
III-V-on-Si GAA devices with a record peak transconductance at 0.5 V has been achieved by optimizing both the channel epitaxy quality and the gate-channel passivation. In search of device technologies beyond FinFETs and GAA-nanowires for sub-0.5-V operations, imec is investigating InGaAs tunnel-FETs (TFETs); homo-junction III-V TFETs achieving a record ON-state current (ION) and superior subthreshold swing have been demonstrated. These results increase the knowledge on the impact of defectivity and channel optimization on device operations, and pave the way to advanced logic devices based on III-V-on-Si for high-performance or ultra-low power applications.
Imec’s R&D program on advanced logic scaling is targeting the new and mounting challenges for performance, power, cost, and density scaling for future process technologies. One of the directions that imec is following looks into beyond-Si solutions, such as integrating high-mobility materials into the channels of CMOS devices to increase their performance, and the integration challenges of these materials with silicon. Gate-all-around nanowire (GAA NW) FETs have been proven to offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels) achieving high carrier mobility are interesting concepts to increase device performance. Tunnel FETs, on the other hand, offering a steeper than 60-mV/decade subthreshold swing, are a promising option for ultra-low power applications.
At IEDM, imec presented gate-all-around InGaAs nanowire FETs (gate length Lg = 50 nm) that performed at an average peak transconductance (gm) of 2200 µS/µm with a SSSAT of 110 mV/decade. Imec succeeded in increasing the performance by gate-stack engineering using a novel gate stack atomic-layer-deposition (ALD) inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length of 50 nm, compared to the reference Al2O3/HfO2 stack.
Imec also presented a planar InGaAs homo-junction TFET with 70% Indium (In) content. The increase of In content from 53 to 70% in an 8-nm channel was found to significantly boost the performance of the device.
“Imec’s R&D enables Moore’s law beyond the 5-nm technology node through three approaches. First, we are tackling the technology challenges to extend silicon CMOS devices towards smaller nodes. At the same time, we research into disruptive heterogeneous solutions for beyond-silicon CMOS devices to increase performance and introduce new functionalities. Lastly, imec pursues emerging beyond-CMOS devices and systems such as spintronics to investigate further functional scaling beyond device-density-driven scaling,” stated Aaron Thean, vice president and director of imec’s advanced logic R&D program. “Boosting the performance of advanced compound semiconductor logic devices is extremely important, and these results support the quest of the semiconductor industry to find solutions that enable 5-nm technology nodes and beyond.”
“ASM and imec have a long history of R&D collaboration using many of ASM’s products and advanced deposition and thermal processes,” said Ivo Raaijmakers, ASM CTO and director of R&D. “As a leader in ALD, we are glad to see this breakthrough new ALD material now demonstrated in imec’s high mobility devices and presented at IEDM 2015.”
Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony, and TSMC.
