Leti develops 3D network-on-chip to improve high-performance computing

July 12, 2016

San Francisco, CA. Leti, a CEA Tech institute, today announced it has developed a new on-chip communications system to improve high-performance computing (HPC) that is faster and more energy-efficient than current solutions and is compatible with 3D architectures.

Leti researchers, working in the frame of IRT Nanoelec, boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure, or by placing the chips side by side on a silicon interposer. The chips, which have progressed from demonstrator to fabrication-ready, exchange data via a new communications network that is part of the network on chip (NoC) called 3D-NoC.

3D-NoC technology has been demonstrated with a homogeneous 3D circuit that comprises regular tiles assembled using a 4x4x2 NoC. It also features robust and fault-tolerant asynchronous 3D links and provides 326 Mflit/s at 0.66 pJ/bit. It was fabricated in a CMOS 65-nm technology using 1,980 TSVs in a Face2Back configuration.

This second-generation 3D-NoC technology has been integrated in the INTACT circuit developed in the frame of IRT Nanoelec. The 3D circuit, currently in foundry, combines a series of chiplets fabricated at the FDSOI 28-nm node and co-integrated on a 65-nm CMOS interposer. The active interposer embeds several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability, and integrated passive components.

Moreover, the chip requires 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct-memory-access-type software used for data transmission and has likely industrial uses in virtual-server migration applications.

“The steady rise in the number of applications that require high-performance computing creates a demand for new hardware-plus-software communications solutions that improve both performance and energy consumption,” said Denis Dutoit, Leti strategic marketing manager. “This new technology brick makes it possible to transfer data between processors via a network-on-chip, delivering more powerful, energy-efficient computing.”

Leti is hosting its annual workshop during Semicon West on “Sensing your Future with Leti” at 5 p.m., July 12. Registration is here.

Leti scientists will be available at booth #2028 in the South Hall throughout Semicon West to discuss this announcement and other recent research developments and initiatives.

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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