Fort Worth, TX. Walden C. Rhines, chairman and CEO, Mentor Graphics, today at the International Test Conference delivered a keynote address titled “The Business of Test: Test and Semiconductor Economics.” He noted that although he runs a design-software company, he has been involved in test since early in his career, and he offered his perspective on when and how test has impacted business with an emphasis on indicators over the years that could have avoided the need for brute-force methods.
In the semiconductor industry, he said, companies compete on price, performance, and power—test is not a differentiator, and test becomes overhead.
He recounted running a microprocessor business within TI in 1979, with 40% of engineering effort being spent on test, generating functional test patterns. An engagement with IBM brought a focus on level-sensitive scan design, or LSSD, which provided a way to break test down into simplified pieces that could be automated. But LSSD wasn’t adopted primarily to boost engineering efficiency but rather to deal with challenges of emulator chips, which were typically one rev behind the ICs they were supposed to emulate. Scan provided a way to solve this problem, at the cost of some silicon real estate. The industry would have been wise to move to scan sooner, Rhines said.
The next revolution in test, he said, was embedded compression. In retrospect the technique is an obvious choice but was speculative and considered risky at the time. However, tester costs were rising at an unsustainable rate. Manufacturing costs per transistor were falling; test costs per transistor were not.
Unfortunately, test compression was introduced in 2001, at the height of the dot-com bubble. When the bubble burst, companies found they had purchased too much test capacity—there was little incentive to pay for test compression with testers sitting idle on the test floor. Eventually, companies worked through the excess capacity, and test compression became a success.
Original test compression rates were about 10X. With a growing need to detect delay defects with transition fault models at the 18-μm node and beyond, at-speed test became no longer optional. Enhanced compression emerged to support the increasing pattern count, which was growing faster than transistor count.
The next innovation was diagnosis-driven yield analysis, which evolved to find systematic defects at smaller nodes. Physical failure analysis was slow and expensive, he said, but “virtual failure analysis” provides millions—not dozens of hundreds—of test observation points. The technique spurred improvement in mature yields.
He cited several other test issues with respect to both technology and business. In the latter category, he noted that foundries had long resisted sharing data with their fabless customers, but such sharing is now a necessity. With respect to technology, he cited the move to 100% analysis of all failed die, cell-aware test, hierarchical test, and requirements for test of automotive ICs, which are often mostly analog. Analog test time dominates mixed-signal test. Ultimately we will improve analog test probably series of innovations, he said.
He wrapped up his address by saying DFT technologies add value, and the value of test data will increase. He said that an airliner generates about 10 TB of data for every 30 minutes of flight, and the data becomes more valuable than a jet engine. Alluding to a “thrust as a service” model, he suggested that a company could give away an engine and just sell a maintenance contract—using the data to monitor aging and degradation and to predict when a device is about to fail. “The value of test data will increase,” he concluded. “Test as overhead becomes test as value creator.”
In response to a question about the recent announcement that Siemens will acquire Mentor Graphics, he said, “We are absolutely delighted.” He called the two companies “totally complementary.” Although one-third of Mentor’s business might seem a good fit for Siemens, the remaining two-thirds relating to semiconductor design might not. However, said Rhines, Siemens views IC design as fuel for the electronic solutions Siemens will be offering.
