Fort Worth, TX. System-level test was the topic of an International Test Conference virtual panel moderated by test consultant Paul Berndt. The virtual nature of the panel converted the audience into panelists, who could respond online to polling questions and provide Twitter-like 140-character comments. Berndt got the session started by explaining that SLT adds to your test flow one more test step after final package test—one that comes as close as possible to representing your application—somewhat like using an actual cellphone as your testbed for testing a cellphone chip, for example.
A plurality of participants cited the autonomous car as a key application area contributing to the demand for SLT, with the move toward 3D integration coming in second. Although not on the virtual survey list, high-speed I/O was volunteered by one participant.
Device complexity was seen by a majority as the biggest driver in the trend toward SLT, with quality requirements coming in a distant second. Only one participant identified insufficient fault models as a driver, while advanced nanometer nodes got two votes.
When asked whether structural and functional test alone can obtain defect-free results without SLT, a decided majority answered “no.”
There was some discussion over whether a component supplier or system integrator should be responsible for SLT. A majority said both should be, with the system integrator alone in second place and the component manufacturer alone in last place.
A clear majority contended that SLT is not a stopgap technology, and a similarly large majority responded that the most typical implementation will be a dedicated system, with a minority suggesting an ATE/hybrid approach. Several participants commented that you don’t want to tie up an expensive ATE system while waiting for a processor to boot up, for example, during a system-level test.
When asked if it’s practical to integrate SLT into chip-level test, a majority said no. One participant commented that there is more to a system than one chip—there are boards, wires, connectors, cables, software, variable environmental conditions, and other chips.
A clear majority believed that SLT can become cost-effective enough to be more widely accepted, although a plurality see cost as currently being an issue with SLT going forward. Other issues cited included lack of quantifiable metrics and difficulties in fault isolation and diagnosis that could yield useful information to feed back to designers.
Only one person thought that the implementation of SLT could eliminate final test. A strong plurality said SLT would permit the application of fewer test patterns at final test, while an equal plurality said SLT would have no effect on final test. A strong plurality saw an urgent, immediate need for AI-based smart testing and data analytics, with most remaining participants seeing a need over the next five or ten years. A few participants see AI, smart test, and data analytics as “just a bunch of buzzwords and hot air.”
The biggest barrier to SLT adoption was seen as economics followed by implementation complexity. As for industry areas that could be best served by SLT, participants ranked automotive applications at the top, followed by biomedical, data-center, consumer-electronic, and IoT applications.
For more on SLT, you can attend a webinar titled “Key Trends Driving the Need for More Semiconductor System-Level Test.” that I will be moderating on November 29 at 1 p.m. EST. Anil Bhalla and Karthik Ranganathan of Astronics will be the presenters. You can register here.
