TetraMAX II shortens test pattern generation from days to hours

July 13, 2016

Mountain View, CA. Synopsys Inc. on Tuesday announced its next-generation ATPG and diagnostics solution, TetraMAX II, incorporating the innovative test engines unveiled at the International Test Conference in October 2015. Delivering an order of magnitude faster runtime, TetraMAX II cuts ATPG runtime from days to hours, ensuring patterns are ready when early silicon samples are first available for testing. Additionally, TetraMAX II generates 25% fewer patterns, allowing IC design teams to shorten the time and lower the cost of testing silicon parts or, if required by specific market segments such as automotive, increase the quality of test without impacting test cost. Reuse of production-proven ATPG interfaces ensures risk-free, easy deployment into design and test flows. Users are sharing their experience with TetraMAX II at the Synopsys Users Group (SNUG) India conference in Bangalore this week.

TetraMAX II is built on new test-generation, fault-simulation, and diagnosis engines that are extremely fast, exceedingly memory efficient, highly optimized for generating patterns, and capable of executing fine-grained multithreading of the ATPG and diagnosis processes. These innovations lead to significantly fewer test patterns and cut ATPG time from days to hours. The memory efficiency of TetraMAX II enables utilization of all server cores regardless of design size, surpassing previous solutions that are limited by high memory usage. The reuse of production-proven design modeling and rule checking infrastructure, as well as user and tool interfaces, ensures designers can quickly deploy TetraMAX II risk-free on their most challenging designs. Moreover, TetraMAX II utilizes established links with Synopsys Galaxy Design Platform tools, such as the DFTMAX solution, PrimeTime timing analysis, and StarRC extraction tool, and other Synopsys tools, including Yield Explorer yield management and Verdi debug tools, to deliver the highest quality test and the fastest, most productive flows.

“Designers worldwide rely on Synopsys’s synthesis-based test solution to achieve the highest test quality on their most challenging designs,” said Antun Domic, executive vice president and general manager for Synopsys’s Design Group. “TetraMAX II demonstrates our commitment to continually deliver innovative and groundbreaking test technologies and addresses our customers need for faster ATPG and diagnostics as well as reduced silicon test time.”

The Synopsys synthesis-based test solution comprises DFTMAX Ultra, DFTMAX, and TetraMAX I and II for power-aware logic test and physical diagnostics; DFTMAX LogicBIST for in-system self-test; SpyGlass DFT ADV for testability analysis; the DesignWare STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System for embedded test, repair and diagnostics; the Z01X fault simulator; Yield Explorer for design-centric yield analysis; and the Camelot software system for CAD navigation.

Synopsys’s test solution combines Design Compiler RTL synthesis with embedded test technology to optimize timing, power, area, and congestion for test as well as functional logic, leading to faster time-to-results. The Synopsys test solution delivers tight integration across the Synopsys Galaxy Design Platform, including Design Compiler, IC Compiler II place and route, and PrimeTime timing analysis, to enable faster turnaround time while meeting both design and test goals, higher defect coverage and faster yield ramp.


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