Last month's Design Automation Conference in San Diego was a great place to tap into the energy and enthusiasm that is revitalizing the world of semiconductor design. Based on the signs, the next couple of years will be very fertile in terms of innovative chip designs in all flavors: ASICs, FPGAs, and ASSPs.
At too many trade shows, the exhibitors stand around and talk among themselves. But at DAC, exhibitors representing more than 200 companies found their booths and their accompanying demo rooms (integrated on the show floor for the first time) were packed with chip designers wanting to get the latest on design automation tools.
With the show in its 42nd year, I am an admitted DAC newbie, this being my sophomore foray to the event. I walked away from it overwhelmed by the array of tools that many of you rely on to tackle your daily design challenges. And I'm not even talking about the smarts it takes to actually use the tools. Just sorting through the options and selecting the right tools while understanding how they work together is an amazing task in itself!
DAC included many new vendor alliances that potentially will make it easier to choose certain product families. Yet many of you say you don't want to be "locked in" to a particular proprietary tool set. Rather, you're on the hunt for "best in class" and want the freedom to mix and match to get to the ultimate tool set. Putting the right tools in your box gives you the control you need to meet the challenge of optimizing sometimes conflicting design goals, such as power, speed, leakage, yield, die size, and cost.INTEL CTO'S VIEW This ability to "optimize globally" is more vital than ever before. According to Patrick Gelsinger, Intel's CTO and DAC's keynoter, the key to meeting tomorrow's design challenges will be simultaneously optimizing for multiple variables, rather than optimizing for any single element. In the past, Gelsinger said, designers mainly focused on optimizing for maximum transistor density—i.e., packing in as many transistors into the smallest space possible.
Gelsinger said that designers need to start considering that this generational scaling to new geometries is a given (that "transistors are free"). The only real limiter of Moore's law is power, he said, which on the other hand is "not free." At smaller geometries, new random variances such as nano-effects and challenges in power leakage emerge and pose problems for traditional design tools. One counterintuitive solution to the new hurdles of complexity, cost, and power may be to reduce power density by "spreading things out," said Gelsinger. The bottom line, he believes, is that "designers will need to optimize for multiple variables simultaneously, as opposed to optimizing for any single element."
Our EDA specialist David Maliniak, who presented all the EDA trends in a live Showcast from DAC, points to power integrity as one of two dominant themes at the show this year. He believes that power integrity is fast becoming the pivotal design issue for many designers and therefore to EDA vendors. The other hot-button, he said, is that electronic system-level (ESL) design has arrived at long last. There's "a ton" of startups in the ESL area, he noted. At the same time, more established vendors such as CoWare and Summit are gaining traction. With so many 90-nm designs soon to be coming down the pike, designers are coming to the realization that they must move up in abstraction of their designs "or they will never tape out," he said.
Our other special guest for the DAC webcast was Gary Smith, Gartner Dataquest's highly respected chief EDA analyst. Smith also sees designers starting to make the move up in abstraction to ESL with back-end layout teams growing to manage the complexity.DAC HIGHLIGHTS IN WEBCAST For more of David's and Gary's insights and lots more product and show highlights (if anybody saw the whole show at DAC, it's these guys!), check out the DAC Showcast, which we produced live from the event. To view the Showcast yourself, log on to our archive at http://planetee.com/events/.