Flow control signals
The typical RS232 transceiver interface IC found in many embedded systems generates ±6-V line-level signals. While these signals aren’t intended to deliver power, in certain situations it’s possible to scavenge sufficient energy from them to power a connected device.
A discrete version of the power-scavenging interface establishes a local positive supply from the flow control signals (Fig. 1) DTR and RTS. When asserted, RTS and DTR charge capacitor C1 through diodes D1 and D2 to create VPOS. The linear voltage regulator IC (U1) converts VPOS to establish a logic-level power supply, VCC, at a fixed 3.3 V, to power an attached microcontroller or other interface circuit.
The transmit data signal TXD, which is negative when no data is in transmission, creates the local negative supply in a similar way. The non-asserted TXD charges capacitor C2 through diode D3 to create VNEG. When data is in transmission, diode D3 blocks the positive voltage pulses from the negative supply rail. The specified Schottky diodes minimize the forward voltage drop between the RS232 signal lines and the power rails.
The remaining circuit elements provide level-translation and logic-level conversion for the serial port signals ROUT and TIN. Transistor Q1, an N-type enhancement MOSFET, generates ROUT from the incoming RS232 transmit signal TXD, using a divider (R1 and R2) to limit the gate voltage. The drain resistor (R3) ensures a logic-high output when TXD is inactive.
To convert the microcontroller’s returning logic-level signal (TIN) to an RS232 signal, a non-inverting, tri-state output buffer (U2) and a pull-up resistor first expand the signal’s voltage to range from GND to VPOS. Transistor Q2, a P-type enhancement MOSFET, then inverts and expands this intermediate signal to an output signal (RXD) that ranges between VNEG and VPOS.
Tests of the circuit, using a desktop PC to provide the host serial port, validated that it could support serial communication data rates up to 115,200 baud. An alternative design, for use in cases where higher data rates are needed (up to 1M baud), uses ICs as the active components (Fig. 2). This approach modifies an LTC2801 RS232 transceiver IC from Linear Technology (U1) to deactivate the device’s internal charge-boost circuitry.
Tying the VCC, CAP, and SW pins to ground deactivates the charge-boost. Furthermore, it provides the additional benefit of eliminating the need for external charging components. Instead of internally generating the RS232 bias-voltage levels, U1 receives the bias voltages VPOS and VNEG, which arise from the incoming RS232 signals as in the discrete design.
The positive supply (VPOS) also connects to a linear voltage regulator IC (U2), configured via R1 and R2 to generate a 2.5-V supply rail. This regulated output provides the logic-level supply bias for the transceiver. The scavenged and regulated supply also provides power to an attached microcontroller or other interface circuit, while U1 provides the level translations for ROUT and TIN.
Ultimately the available current on each RS232 signal line will limit the circuit’s overall performance. At a nominal 6-V supply and with an EIA-232 specification load of 3k, a reasonable expectation is to scavenge 2 mA per line. Because the transceiver’s current consumption is in the tens of micro-amps, most of the scavenged energy is available to power the attached circuitry. More power is available, however, at the cost of degrading the RS232 signal amplitude.
For example, in testing with an HP IPAQ 5900 series PDA, we observed a positive load current of 4 mA per pin at the reduced RS232 signal amplitude of 4.5 V. This is sufficient to activate a low-power microcontroller and several attached sensors.