The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The methodology, which melds Denali's Databahn DDR controller and PHY IP with the Encounter technologies, enables designers to achieve DDR memory-system implementations at 65 nm and at speeds exceeding 400 MHz.
Some 70% of new SoC designs now use DDR-memory-subsystem IP. DDR memory systems with high system-performance requirements have become a critical factor for products in the networking, computing, and consumer-electronics segments, where memory bandwidth is a key element in achieving system performance.
In addition, due to dramatic increase in clock speeds and the challenges of 65-nm implementation, the ability to implement DDR-PHYs and quick closure on timing has become a serious bottleneck regarding time-to-market. Some of the world's largest IDMs have declared this as their number one problem. Denali has standardized on SoC Encounter and Encounter Timing System for DDR-PHY design, physical implementation, timing closure, and signoff analysis. Thus, Denali now offers DDR-PHY design kits, methodology services, and hardened IP to its customers.
A Webcast providing a more comprehensive overview, highlighting the benefits of this joint methodology, can be viewed at: www.denali.com/webcast/socencounter
Cadence www.cadence.com
Denali Software www.denali.com
