Sandy Creek integrates graphics on-chip
Tunnel Creek uses PCI Express for all peripherals
The Intel Developer Forum (IDF) kicked off with the usual fanfare highlighting multicore, connectivity and security. The chips on the docket include Sandy Bridge (Fig. 1) targeted at the mainstream and its Xeon server sibling, Ivy Bridge. Embedded developers will also appreciate the new Atom platform, Tunnel Creek (Fig. 2), that foregoes a proprietary frontside bus with PCI Express allowing for a range of connectivy options including easier intergration with FPGAs.
Multimedia demonstrations were front and center for the initial keynote presentations by CEO Paul Otellini and Dadi Perlmutter, executive vice president and general manager of Intel's Architecture Group. One major element of these demos was to highlight the AVX for Advanced Vector Extensions (see Intel's AVX Scales To 1024 bit Vector Math). AVX impacts not only multimedia but vector processing and encryption as well. The AES encryption support was highlighted by a video conferencing demo using encrypted links. There was not much to see other than the fact that the demo was extremely smooth and using hires cameras. It is not surprising that Cisco's Cius video conferencing platform was one of the vendors presented during the keynote. Another hint of things to come was the expanded use of Turbo Boost for the multimedia side of things as well as pushing multiple cores past the thermal TDP as required.
Tablets and Smart TV were also on the agenda. I'll leave tablets to a later date other than to mention Intel's support for MeeGo, a common multimedia platform for all things Intel.It is a challenger to Android. Sony was the vendor on display with its version of the soon to be released Google TV. An entire venue at IDF was dedicated to essentially Internet TV, an idea whose time may have finally arrived. Unfortunately the limiting factor is still on the content provider side, not on the hardware side. Still, HD video will be the norm when it finally arrives.
I'll wrap up with a short comment on the promise of the Westmere-EX platform. This chip is likely to show up in 2011 with 10 cores and hyperthreading support for a totol of 20 threads.