Electronic Design

EDA Rides The PCI Express

A spate of IP rollouts takes PCI Express from the theoretical to the practical.

Acceptance of a new standard is a chicken-and-egg affair. Which comes first, acceptance or the wherewithal to accept it? In the case of the emerging PCI Express high-speed interconnect standard for next-generation system design, the EDA and intellectual-property (IP) industry has responded with a flurry of design and verification products, paving the way to broad proliferation of the technology.

Mentor Graphics offers a PCI Express configurable controller core as well as a means for in-circuit emulation verification through the use of its VStation and Celaro emulation systems. A collaboration with Altera has produced a reference design for a PCI-to-PCI Express bridge application. The core available now is a simple fixed-configuration-type supporting PCI Express endpoints and bridges from one to four lanes in width. Scalable versions supporting higher bandwidths will follow. Pricing hasn't been set yet.

Likewise, Synopsys announced implementation and verification IP for the standard through its DesignWare portfolio. Its PCI Express core is synthesizable IP configurable to address applications from desktop systems to mobile devices. Verification IP includes bus-functional models and a user-extensible monitor to validate protocol performance and measure coverage. One-year subscriptions for the verification IP start at $9800; availability is in Q2 of 2003.

Support for PCI Express in Synopsys' OpenVera verification methodology comes from Qualis in the form of Domain Verification Components (DVCs) supporting the PCI Express Base Specification and the draft PCI Express Advanced Packet Switching Specification. The DVCs, which fully support the physical, data-link, and transaction layers, can detect error conditions, catch protocol violations, and check for compliance to the PCI Express standard. Pricing starts at $15,000 for the Base DVC and $20,000 for the Advanced Switching DVC (which includes Base functionality). They will become available in April.

Still looking for verification IP for PCI Express? Denali's PureSpec provides a path to presilicon verification of design compliance with both the standard and interoperability. Within PureSpec, all protocol layers of the PCI Express specification are completely modeled and can be coordinated simultaneously or used separately. It models all devices within the standard's topology, including the root complex, switch, endpoint, and PCI-Express-to-PCI-bridge. PureSpec is available now. Pricing is $5000/year/simulation seat.

Back on the implementation IP side, NurLogic Design has rolled a 2.5-Gbit/s PCI Express PHY core in 0.13-µm technology. The eight-lane OpalLink core is offered as a hard-IP block with support for popular EDA tools and foundry flows. Operating at 2.5 Gbits/s/lane, the core consumes less than 80 mW/lane. It'll be available for licensing in the second quarter. Contact NurLogic for pricing.

Mentor Graphics Corp.

Synopsys Inc.

Qualis Corp.

Denali Software Inc.

NurLogic Design Inc.

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