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32-nm Platform Targets Next-Generation SoCs

Geneva, Switzerland: STMicroelectronics has announced a 32-nm technology platform that enables the design and development of ASICs for networking applications. The system-on-a-chip (SoC) design platform implements the company’s 32LPH (low power, high performance) process technology and relies on the industry’s first serializer-deserializer (SERDES) intellectual property (IP) available in 32-nm “bulk” silicon, STMicroelectronics says.

Enabling very large ASIC designs, greater than 200 mm2, the platform enables a mix of high performance, high complexity, low power consumption, and reduced silicon real estate per functional block. It’s designed to accelerate the development of next-generation networking ASICs used in high-performance applications such as enterprise switches, routers, and servers as well as optical cross-connect and wireless infrastructure applications.

“With the introduction of the 32LPH platform, ST is enabling the next generation of equipment for communication infrastructure applications, which requires highly integrated ASICs that can satisfy the increasing demand in performance, while also meeting extremely challenging power consumption and silicon integration goals,” said Riccardo Ferrari, group vice president and general manager of ST’s Networking and Storage Division. “We are extremely encouraged by the strong interest that customers are demonstrating for this platform, which has already gained key design wins.”

ST’s S12 is a key piece of SERDES IP that has already been successfully demonstrated in labs at selected key customers. The company says that it is vital for the development of ASICs for networking applications while enabling chip-to-chip, chip-to-module, and backplane communications in networking equipment designs. The first ASIC prototypes implemented in ST’s 32LPH process technology are expected early in 2011 with production ramp-up in the second half of 2011.

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