A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2.6-times higher than that of 65-nm CMOS technology. The modeling technique was announced at this week's VLSI Symposium.
Advances in CMOS process technology require shorter gate lengths, and stress enhancement techniques have proven effective as a means to improve transistor performance. However, 45-nm CMOS requires gate length scaling to advance significantly, and the application of stress enhancement techniques will produce complicated variability as a result of dependence on the design's layout. This issue could be worked around in earlier generations by setting an additional design margin for safer design or by restricting the pattern and design. However, this approach is insufficient for 45-nm CMOS technology because it sacrifices improvement in gate density.
Toshiba's newly-developed modeling technique predicts the performance of each transistor individually by accounting for factors dependent on circuit layout. In 65-nm CMOS technology, designers must consider gate length, gate width, and the distance between the gate and isolation area as major factors affecting transistor performance. But in 45-nm CMOS technology, designers must also consider the effects of gate spacing and contact locations.