Electronic Design

MIT Demonstrates 25-nm Lithography

MIT researchers have used a recently developed technique called scanning-beam interference lithography (SBIL) to achieve a significant advance in nanoscale lithography. The team created lines about 25 nm wide separated by 25 nm spaces. By comparison, the most advanced commercially available computer chips today have a minimum feature size of 65 nm. Intel recently announced that it will start manufacturing at a 32-nm line-width in 2009, and the industry roadmap calls for 25-nm features in the 2013-2015 timeframe.

The MIT technique could also be economically attractive because it works without the chemically amplified resists, immersion lithography techniques, and expensive lithography tools that are widely considered essential to work with optical lithography at this scale. Periodic patterns at the nanoscale are notoriously difficult to produce with low cost and high yield, the team noted.

The MIT team includes Mark Schattenburg and Ralf Heilmann of the MIT Kavli Institute of Astrophysics and Space Research, and graduate students Chih-Hao Chang and Yong Zhao of the Department of Mechanical Engineering. Their results have been accepted for publication in the journal Optics Letters and were recently presented at the 52nd International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication in Portland, Ore.


TAGS: Intel
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