Electronic Design

Nikon, Synopsys Offer 45nm Manufacturing-Aware Solution

Nikon Corporation, which supplies lithography equipment for microelectronics manufacturing, said its optical lithography exposure tool data is available for the latest release of EDA giant Synopsys' Proteus optical proximity correction (OPC) software. As part of an ongoing collaboration, the two companies developed an embedded scanner parameter module, which delivers the "manufacturing-aware" OPC and resolution enhancement technology (RET) lithography simulation models needed to make chips at 45nm and below. At these sizes, critical dimension (CD) control takes place at the single nanometer level. Current OPC design tools use idealized models of lithography tools to synchronize with the mask pattern. The pattern can only be optimized by comparing the simulated model to the calibrated exposure results, an approach that may not produce accurate, predictable models, according to a Synopsys release. That's why Nikon and Synopsys collaborated to develop a "manufacturing-aware" OPC solution that provides improved modeling accuracy. The new interface gives Proteus modeling customers access to Nikon's proprietary scanner information, including such higher-order lithographic effects like polarization, flare, synchronization, and various aberration data. This methodology can accurately predict lithographic printing effects previously missed with traditional "idealized" OPC models, according to Synopsys, increasing OPC modeling accuracy and reducing OPC modeling time. "By incorporating our proprietary scanner information into the Proteus software, Nikon customers can gain a competitive advantage with improved OPC accuracy and faster optimization time," Toshikazu Umatate, executive officer of the precision equipment company at Nikon, said in a statement. "Combining proprietary lithography information from Nikon with Proteus mask-synthesis data moves OPC accuracy into a new domain leading to improved CD control at 45 nanometers and below," Wolfgang Fichtner, senior VP and general manager of the silicon engineering group at Synopsys, said in a statement.

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