C-To-Hardware Design Suite Quickly Spins Reprogrammable SoCs

June 10, 2002

The latest version of a Handel C-to-hardware design suite, DK1.1 includes new features for system-level hardware/software co-design, cosimulation support for ARM and PowerPC embedded processors, improved synthesis, enhanced area and delay analysis, and more. The suite supports the design, validation, iterative refinement, and implementation of complex algorithms in hardware.

It includes built-in design entry, simulation, and synthesis, all of which are driven by the Handel C design language. Handel C is based on ANSI C, but it's extended with concepts for timing, concurrency, flexible-width variables, and resource allocation to let software engineers and hardware designers quickly implement complex algorithms in hardware. Reprogrammable system-on-a-chip (SoC) designers can make informed critical decisions about hardware/software partitioning using a what-if scenario. A mixed-language facility enables calling of C/C++ functions as well as use of C/C++ testbenches to verify Handel C designs.

Platforms include Windows, Sun Solaris, and Red Hat Linux. New licenses start at $35,000.

Celoxica Ltd.
www.celoxica.com; +44 (0) 1235 863656

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.