If there's a truism in design debug and
test, it's that the earlier you can find a
bug, the less costly it is to fix. Thus,
finding bugs at RTL is far preferable to
finding them after synthesis. With
DeFacTo Technologies' HiDFT-Scan,
designers can analyze their RTL IC and
system-on-a-chip (SoC) designs, create
the appropriate scan-test structures, and
insert them into the RTL code.
HiDFT-Scan works within existing
design flows and with industry-standard
synthesis tools. By eliminating the need
for gate-level scan, HiDFT-Scan enables
a high-level design-for-test (DFT) sign-off
methodology (see the figure).
The ongoing shrinkage in feature
sizes at nanometer scales has made
designs so complex that it's no longer
realistic to perform verification at gate
level. After synthesis to gates, the late
implementation of any logic, including
scan chains, has a significant impact on
design choices and the overall project
schedule. Additionally, it can adversely
affect the ability to meet timing, power,
and clock-speed goals.
HiDFT-Scan permits designers to create
a high-level DFT signoff methodology, closing
the gap between RTL and DFT. It allows
the implementation of all DFT-related logic
at the same stage at which primary design
decisions are made, facilitating early identification
of test issues. It also speeds up
RTL simulation and formal verification
because simulations can be run on the
design after scan is inserted but before
synthesis. HiDFT-Scan generates RTL scan
testbenches, enabling designers to proceed
with both design verification and testrelated
corrections before generating the
gate-level netlist, as well.
Furthermore, the methodology that's
afforded by HiDFT-Scan enables designers
to avoid the insertion of additional
test structures on critical paths after synthesis.
Users can augment their existing
signoff methodologies at RTL with capabilities
such as RTL analysis of test structures
and management of power consumed
by testing.
DeFacTo Technologies
www.defactotech.com
