µP Architecture Delivers 600 MIPS AT 300 MHz

July 1, 2001

Expanding the company's 64-bit MIPS RISC product offerings, the VR5500 microprocessor incorporates a new, flexible and scalable architecture that enables it to deliver 600 MIPS at 300 MHz, said to be one of the highest MIPS:MHz ratios in the industry. This architecture for scalable performance promises future versions of stand-alone processors with speeds up to 800 MHz. The heart of the processor is its two-way superscalar micro-architecture with dual instruction issue, out-of-order execution and a 10-stage, decoupled super pipeline. The architecture contains six independent execution units, including two integer units, two floating-point units (FPUs), a non-blocking load/store unit, and a branch unit. This design provides 10 stages operating at up to 400 MHz, and, to maximize the instructions issued and executed per cycle, the architecture supports 16 renaming registers and out-of-order execution. The processor's 64-bit system bus supports speeds up to 133 MHz and also provides an optional 32-bit mode. And the micro-architecture delivers over 600-Dhrystone 2.1 MIPS and up to 150 MFLOPS at 300 MHz. Other features include a detachable execution unit architecture, built-in debugging mode, 32 KB non-blocking instruction and data caches that support cache line locking and write-back and write-through, and 1.5V core and 3.3V I/O operation. The VR5500 architecture also implements an enhanced version of the MIPS-IV instruction set architecture. Extensions include three-operand multiply instructions and integer multiply-add instructions to support digital-signal processing applications. In addition, 32- and 64-bit rotate-and-count leading 1/0 instructions are included to support printing and imaging applications.Samples of the processor will be available in the third quarter of 2001 in a 272-ball advanced BGA package. Though subject to change, price is expected to be $35 each/10,000

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