Silicon-Versus-Layout Tool Confirms RET Closure

June 7, 2004

Nanometer designs require new approaches to silicon-to-layout verification (SVL). Widespread use of resolution enhancement technology (RET) techniques has led to far greater silicon complexity. Synopsys' latest enhancements to its SiVL tool enable users to achieve what the company calls "RET closure," or having a design's original layout match its silicon image.

The key to RET closure is SiVL's ability to accurately model silicon well before lithography errors make their way into masks and wafers. SiVL achieves high error coverage using modeling technology proven in Synopsys' Proteus optical proximity correction (OPC) tool. A check-figure capability lets the tool run simulation only on the features most likely to have lithography problems leading to yield issues. This same capability allows the tool to build a library of critical-feature checks.

SiVL is now geared to be linearly scalable across compute farms using distributed processing capabilities. It again borrows from Proteus OPC by adopting technology that has enabled Proteus to be used in a 1000-processor computer farm. The result is accurate and thorough silicon simulation in greatly reduced turnaround time.

The SiVL silicon-to-layout verification tool starts at $90,405 for a one-year technology subscription license. It's available now.

Synopsyswww.synopsys.com

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.