Verification Platform Speeds Simulation And Emulation

Aug. 6, 2001
R>epresenting a multifunction verification platform that provides both simulation acceleration and in-circuit emulation capabilities, the Palladium ASIC design verification system dramatically increases designer productivity. It offers compile...

R>epresenting a multifunction verification platform that provides both simulation acceleration and in-circuit emulation capabilities, the Palladium ASIC design verification system dramatically increases designer productivity. It offers compile speeds of 4 million gates/hour on a single workstation.

The system's complete range of verification options includes easy integration into existing software testbench environments. It provides accelerated cosimulation with C/C++, behavioral testbenches, Cadence's NC-Sim logic-simulation environment, Cadence's Signal Processing Worksystem, and third-party testbench products. Also, it may be used for synthesizable testbench acceleration, vector regression, and in-circuit emulation.

A high-speed, transaction-based, cosimulation interface dramatically increases simulation-acceleration performance. Traditional accelerated cosimulation performance is limited by the frequency and latency of communication between the design and the testbench. Palladium's transaction-based interface overcomes this limitation by optimizing traffic and minimizing channel latency.

A high-speed compiler optimizes RTL-to-verification with compile times of 4 million ASIC gates/hour on a single workstation. It also supports concurrent use by simulation and emulation users. The rapid compile time effectively increases the available debug time per user while concurrent use lets multiple users debug chips simultaneously. As a result, designers can find and fix more bugs each day.

All functions, from RTL compilation through simulation acceleration, cosimulation, and in-circuit emulation, are controlled from one GUI. The system incorporates Quickturn's advanced compiler technology with a custom emulation IC. It's expandable to support up to 16 million ASIC gates.

Depending on user configuration, pricing starts at $0.35 per gate. Shipping begins in the fourth quarter of 2001 with support for the HP-UX, IBM-AIX, and Sun Solaris platforms. Palladium also will be available through QuickCycles, a turnkey program providing remote access on a pay-as-you-go basis.

Quickturn, a Cadence company, 55 West Trimble Rd., San Jose, CA 95131; (408) 914-6000; www.quickturn.com.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

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