HDL Simulator Increases Compilation Speed Up To 300%

Rivaling the performance of workstation products, the newest version of the company's HDL-simulation software, Active-HDL 3.6, has been enhanced to increase compilation speeds by up to 300%. The new release includes multiple simulation kernels and new algorithms for library calls that provide a 180 to 300% increase in performance at the behavioral-, structural- and timimg-simulation levels over the previous 3.5 version. To accomodate large designs, a more effective library structure and an improved internal-tables architecture are employed to reduce memory requirements by 30%. Also, the latest vendor-specific libraries have been added including the Xilinx CoolRunner CPLD family and the Virtex-E library of FPGA devices.The application is free to all Active-HDL users with valid maintenance contracts.