COT Design Kit Gets Fabless Houses Into 90-nm SOI

Sept. 15, 2005
Silicon-on-insulator (SOI) promises greater speed and lower power consumption than bulk CMOS processes. But it has been unavailable to the fabless semiconductor world—until now. Thanks to a customer-owned-tooling (COT) SOI design kit from SOISIC, S

Silicon-on-insulator (SOI) promises greater speed and lower power consumption than bulk CMOS processes. But it has been unavailable to the fabless semiconductor world—until now. Thanks to a customer-owned-tooling (COT) SOI design kit from SOISIC, SOI technology proven on Freescale Semiconductor's 90-nm SOI process is now available to the mainstream market.

The kit consists of multi-Vt standardcell libraries, memory compilers, and standard I/Os for manufacturing on the Freescale process. Compared with bulk CMOS processes, it offers a 30% to 40% speed improvement, a 2X power consumption drop, and an area reduction of up to 10% (see the table). SOI technology draws its speed from improved transistor performance. Power-consumption gains result from lower capacitance, much lower leakage current, and smaller cell sizes.

Bulk CMOS processes are expected to fail at the 65-nm mode. So, a move to make SOI available beyond large integrated-device manufacturers (IDMs) is necessary to maintain the process-technology curve. SOI already is a mainstream technology, with AMD's processors, PowerPC chips, and all of the major video-gaming platforms driving volume.

With the SOISIC design kit, systemona-chip designers can work with their industry-standard EDA tool flows. No specific tools or retraining of design engineers are required. All SOI-specific effects are handled at the intellectualproperty level, which makes them fully transparent to users.

SOISIC
www.soisic.com

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