Among the issues compounding
design closure, none is more
pressing than the timing, power, and signal-integrity (SI) loop. Timing
tools have not scaled with design complexity. Runtimes for SI tools can stretch
beyond 24 hours. With hundreds if not
thousands of timing violations to clear
in a given design before tapeout, tools
must evolve to a higher level.
To take timing analysis to the next
level of efficiency, CLK Design Automation's Amber Analyzer boasts an architecture that leverages multicore, multiprocessor compute platforms to
execute analysis runs 10 times to 20
times faster than other timing analyzers
(see the figure).
Everything in the tool's architecture is
threaded, including engines, solvers,
parsers, database management, and
storage. The multimode analyzer digs
into leakage power and statistical leakage power. There's also support for on-chip variation and statistical timing.
The Amber Analyzer addresses the
need for fully incremental operation
across all classes of analysis (timing, SI,
and leakage) for any type of design
change, including cell swaps, netlist
modifications, constraints, or parasitics. Thus, a 50,000-cell swap on a 10
million-instance design takes less than
three minutes to analyze for signal
integrity. Further, the tool's incremental
capability guarantees that the answer it
delivers is the same as if the entire
design had been run flat.
Turnaround time for incremental
analysis is proportional to the size of
the design change. So is the memory
footprint for the analysis. As a result,
incremental jobs can be run on desktop-class machines.
The Amber Analyzer runs on 32-bit
and 64-bit Linux platforms and starts at
$25,000 for a one-year license. An
open C-based API lets users incorporate
the analyzer into other tools.
CLK Design Automation
www.clkda.com
