SystemVerilog Verification Reaches For Higher Productivity

    March 29, 2007
    In its continuing efforts to harness the considerable verification power of SystemVerilog, Synopsys has rolled out extensions to the verification methodology spelled out in its System Verilog Verification Methodology Manual (VMM). The three component

    In its continuing efforts to harness the considerable verification power of SystemVerilog, Synopsys has rolled out extensions to the verification methodology spelled out in its System Verilog Verification Methodology Manual (VMM). The three components, VMM Planner, VMM Applications, and VMM Automation, are intended to make it easy for verification engineers to develop and deploy VMM (see the figure).

    Current methods for SystemVerilog verification planning and tracking are largely ad hoc. Often, they involve spreadsheets and other non-machine-executable formats that cannot back-annotate a verification plan nor enable the measurement and tracking of verification progress.

    VMM Planner permits users to define and execute a hierarchical verification plan. Displayed in a familiar spreadsheet format, the plan can be tracked using multiple user-defined metrics such as coverage of assertions or finite state machines. VMM Planner runs in concert with simulation while coverage metrics are automatically back-annotated into the spreadsheet, eliminating error-prone manual intervention.

    VMM Applications addresses test-bench development productivity. The register abstraction layer includes built-in tests for register verification. It also facilitates quick response to register specification changes. The hardware abstraction layer includes pre-built interfaces for linking the test-bench to emulators and accelerators. A memory allocation manager aids in memory subsystem verification.

    Finally, the VMM Automation component consists of tools that automate various aspects of advanced verification. Key among these tools is a VMM-to-SystemC transaction-level interface (TLI) that lets users plug SystemC transaction-level models (TLMs) into their VMM environment.

    Also under the umbrella of VMM Automation is Test Composer, a user interface for quickly creating test scenarios as well as an overall verification environment from an easy-to-use interface. VMM-aware debug enables users to consider methodology when performing debugging. Rather than debugging simple signals, it allows debugging to be done in terms of VMM transactions and data types.

    VMM Planner, VMM Applications, and VMM Automation will be a part of Synopsys' VCS functional verification suite and Pioneer-NTB test-bench automation tool. VMM Planner and VMM Applications are available now in beta. VMM Automation tools will become available over the next 12 to 24 months.

    Synopsys
    www.synopsys.com

    About the Author

    David Maliniak | MWRF Executive Editor

    In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.
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