This year will see the broad emergence of 22-nm semiconductor processes and the beginning of an era in chip design of performance scaling versus geometric scaling. At 22 nm, innovations such as FinFETs and double patterning make for a staggering level of process complexity. Lithography mask counts have gone from around 20 to around 45 in the last 12 years. The number of front-end process steps is now in the range of 500.
These developments have led the International Technology Roadmap for Semiconductors (ITRS) to term front-end process modeling as a “grand challenge” in its 2011 Executive Summary. Semiconductor manufacturers simply need a means of modeling these incredibly complex front-end flows.
Coventor, known best for its MEMS design tools, has updated its SEMulator 3D modeling tool to meet the needs of SoC designers for these advanced process nodes. SEMulator 3D essentially performs virtual fabrication of your system-on-a-chip (SoC) design, obviously in 3D, which will come in handy when you begin designing with structures such as FinFETs.
As inputs, the tool needs a 2D layout, which is usually in the form of a GDSII file imported from the layout tool. The other key input is a process description, most often in the form of a process deck or recipe. These inputs are fed into Coventor’s Voxel modeling engine, which builds up the 3D model.
The tool captures the entire process sequence, whereas some technology-CAD (TCAD) tools might model only a few selected steps. In doing so, it stands a much higher chance of accurately predicting defect modes.
Once users have built the 3D model, it’s a relatively easy matter to simulate the process to determine what changes need to be made to the recipe to ensure that the end product would pass design rule checks. This simulation process resembles conventional circuit modeling, says Ken Greiner, architect and manager for the SEMulator 3D product.
“I think of the tool as behavior modeling for process technology,” says Greiner. “It’s to process modeling what HDL is to circuit modeling, a higher level of abstraction than either TCAD process simulation or ab-initio modeling. We abstract away some of the physical aspects and emulate them with behavioral models.”
SEMulator 3D’s capabilities include process modeling for a 32-nm FinFET SRAM cell and behavioral deposit modeling to enable detection of void pockets. It also can perform behavioral lithography modeling, capturing the differences between the mask set’s geometries and what actually is printed on a wafer (see the figure).
Applications generally will be found in three areas: process integration, design for manufacturability (DFM), and physical simulation. In the first use case, designers are better prepared to change the dimensions of transistors to achieve proper circuit timing through simulation. In DFM, the tool helps users understand process assumptions and ground rules, both of which feed into the construction of process design kits (PDKs). It also can help with understanding the ramifications of patterning choices.
The 2012 release of SEMulator 3D is shipping now.
