High-Speed, High-Gate-Count CPLDs Embed FIFO Control

July 1, 1999

With the potential to cram up to 350,000 usable gates on a single die, Delta39K complex programmable logic devices (CPLDs) are said to be roughly ten times the size of today’s largest CPLDs. Also embedded on-chip is extensive memory (240 Kbits for the 100,000-gate Delta39K100) and FIFO control and dual-port memory arbitration logic for each specialty memory block—the latter two features are said to be firsts for PLDs. Further adding to Delta39K’s cutting edge performance are a blazingly fast, 6.5-ns pin-to-pin propagation delay and 300-MHz system performance—reportedly more than fast enough to implement a fully synthesizable, 64-bit, 66-MHz PCI core—and a programmable, spread-aware PLL with multiply, divide and clock-edge control options to provide four global clocks to all logic clusters, memories and I/O cells to maintain precise on- and off-chip timing. Device power dissipation also is said to be very low (i.e.,

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