System-on-a-chip design is becoming far more difficult and more expensive with each new generation of process technology. Chip complexity is increasing dramatically and, consequently, so is the amount of manpower and time needed to produce a working chip. With manufacturing costs for 130-nm processes skyrocketing, designers need prototyping to manage IC complexity and costs.
Currently, three approaches are used for prototyping, the first being register transfer level (RTL) prototyping. Here, small blocks are quickly synthesized and partitioned with minimal logic optimization.
The second method is physical prototyping, which includes preliminary placement, power-grid planning, and clock estimation.
Unfortunately, neither approach passes viable information to the final physical design and validation tools. As a result, the designer must start all over again with the physical design tool, which won't necessarily follow the information from the prototyping tools.
A third approach combines high-capacity synthesis, prototyping capabilities, static timing analysis, design for test, and power analysis. With it, designers can build and analyze large prototypes that accurately portray their design in silicon and pass information to physical design. The result: a clean handoff and a more predictable path to timing closure, minimizing IC development costs.
