ESL Simulator Enables Rapid Software Iterations Through Validated Code

July 6, 2006
Almost all electronic-system-level (ESL) simulation environments contain models at various levels of abstraction and accuracy. These models can range from behavioral level through instruction level, transaction level, cycle-accurate level, an

Almost all electronic-system-level (ESL) simulation environments contain models at various levels of abstraction and accuracy. These models can range from behavioral level through instruction level, transaction level, cycle-accurate level, and bus transactors on up to RTL.

Developers trying to validate software on a system model must iterate through all their previously validated code when adding new functionality or debugging problems that may have shown up many hours into a simulation run. In a non-homogeneous environment, throughput can really suffer. That's a problem in an iterative process. Moreover, the underlying system model of the hardware components is usually a high-performance one but not cycle-accurate. So developers are often limited in the number of iterations they can run until they get working silicon, and most of the time, that's too late.

In the latest edition of its virtual system prototyping environment, Carbon Design Systems thinks it has a way around this bottleneck. Carbon's Replay technology removes the barriers to incorporating models right up to the RT level in ESL simulations by enabling rapid iterations through validated code and interactive software debugging, all while maintaining the underlying cycle accuracy.

The technology works by running the Carbonized IP in a system-level simulation in the Carbon prototyping environment. The primary IP I/O is saved until a checkpoint, at which the IP models states are saved. Simulations then can be replayed at extremely high speeds to this checkpoint, where the IP models states are reloaded and the simulation can continue from that point.

The Replay technology can have a huge impact on the productivity of software validation. Assuming that a bug in the software is found every two hours of simulation time, rerunning for each bug can take up to 500 hours without the Replay technology. With it, though, getting through the full simulation run takes just 44 hours.

For further information on the Replay technology and the Carbon SOC-VSP environment, contact the company directly.

Carbon Design Systems
www.carbondesignsystems.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

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