Pre-Silicon Validation Tool Adds VHDL Support

SpeedCompiler and DesignPlayer products for pre-silicon chip and system validation now support VHDL and mixed-language designs. Support for VHDL and mixed languages is part of a broad strategy on developer Carbon Design Systems' part to enable designers to deploy a single executable model of their design, even though it may combine VHDL, Verilog, and C.

"It wasn't real difficult for us to add VHDL support," says Alan Swahn, Carbon's director of marketing. But doing so was a key component in Carbon's unfolding strategy to expand into the European market. VHDL support was a matter of adding a parser from Interra Systems. The parser operates on the VHDL-language input and parses it into a data structure used internally by Carbon's SpeedCompiler, which then generates a DesignPlayer validation engine.

Additionally, Carbon recently announced integration with Virtutech's Simics instruction-set simulator (ISS). Sun Microsystems has used Carbon's tools with the Simics ISS. In Sun's case, the ISS was used to model a Sparc CPU, while a DesignPlayer was used to model a host-bus-to-PCI-bus processor.

Sun's engineers were able to boot Solaris on this combination of virtual hardware and run their application code. What's significant is that they found many bugs in the code using the DesignPlayer. But when they modeled the system with the behavioral model for the bus processor that came with the ISS, these bugs didn't turn up. "They were being masked by the abstraction of the behavioral model," says Swahn.

Annual subscriptions for SpeedCompiler are priced from $200,000 to $350,000. DesignPlayer engines for development cost $10,000 per seat in volume, and engines for IP deployment are under $2000 per seat in volume.