Happy With Your Current Verification Environment? Survey Says: No

May 22, 2006
Only 63% of respondents were satisfied with their current verification environment. These environments ranged from HDL simulation (63% of survey respondents) and FPGA prototyping (19%) to emulation (17%).

Where better than the annual EDS Fair to survey the electronics industry to get a feel for electronics design trends in Japan and understand the tools needed to make designers more effective and productive? Where indeed? EVE polled more than 900 EDS Fair attendees who stopped by our booth in January, and some surprises sprang up from the 580 samples used to compile the survey that’s intended for internal planning purposes.

Taking part in the survey were 19 of the top electronics companies in Japan, including five top Japanese system houses and integrated device manufacturers (IDMs). Furthermore, 32% were RTL designers, and 27% were either computer-aided-design (CAD) managers or verification engineers. Another 10% considered themselves managers, while 8% said their role was systems designer.

Our first surprise? Only 63% of respondents were satisfied with their current verification environment. These environments ranged from HDL simulation (63% of survey respondents) and FPGA prototyping (19%) to emulation (17%).

We found that 27% believe emulation is a viable co-design solution, while 33% named ESL design software as the means to effective co-design. In addition, 14% of those surveyed noted that virtual prototyping is co-design, while 12% defined it as prototyping.

In a related question, 54% wrote that they have not purchased co-design solutions for hardware/software design, while 19% said they had. A mere 26% had yet to purchase co-design solutions, but indicated that they may in the future.

Another surprise? Assertion-based design is used by 41% of respondents, with cycle-based simulation weighing in at 32% and transaction-based verification being unsatisfactory to 19%.

Interestingly enough, 30% of those evaluating emulation solutions claimed that speed is a reason for including it in a verification environment, while 29% said it would be useful for hardware/software co-validation. Also, 21% believe it’s useful for debugging, whereas 5% noted that it can be used to accelerate the design cycle.

Finally, those surveyed were asked why their verification methods were not satisfactory. It’s too time-consuming according to 39% of respondents, while 20% said it’s not accurate enough. Expense is a concern for 16%, and 12% said it’s not worth the bother. And, 7% said that a verification methodology is too hard to reuse.

This survey validated many of our assumptions, but it points to an inescapable conclusion: There’s a desperate need for the EDA industry to produce verification tools that can make a designer more productive. At EVE, we’ve taken up the challenge. The question remains: Has the rest of the EDA industry? And if it hasn’t taken up the challenge, then why not?

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