PLLs Slash Cost Of Network Clock Design

Nov. 1, 2000

Claiming to reduce the cost of designing industry-standard clocks used in multi-platform network equipment by up to 50%, the MT9045 digital phase locked loop (PLL) chip is the first in a family of 3.3-volt digital PLLs that regulate the critical timing function in central office and customer premises equipment. This standard PLL chip that supports multiple synchronization standards, simplifies clock design, and is said to reduce the cost of Stratum 3 clocks from $300 to less than $150. The MT9045 and MT9043 are digital PLLs switch the source of the timing signal from a failed interface to an operational interface without causing a loss of data. The MT9045 is a reference-switching PLL with a specialized frequency holdover capacity. Also a reference-switching PLL, the MT9043 is used in Stratum 4E clocks, commonly used in line-timed T1/E1 networking equipment with more than one network interface. All three devices operate at 3.3V and can be combined with firm's switching chips and T1/E1 framers. Supplied in 48-pin SSOPs, the MT9040 is priced at $12.00, the MT9043 is $17.04, and the MT9045 is $37.74 each/1,000.

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