Never in my wildest dreams did I think that the Verilog hardware description language (HDL) would spawn an industry and be a fixture of electronics design for more than 15 years. HDLs were a replacement for schematics in the late 1980s. The key benefit of the HDL was that it represented a more compact version of the design than gates on a screen. If designers can understand more of the design looking at a single screen, they can debug it much more efficiently, which increases productivity. Productivity gains were dramatic in those days for designers using Verilog.
Curiously enough, the original driver behind Verilog was support for the test space, and early synthesis for design. However, the emerging ASIC market provided the Verilog HDL and its producer, Gateway Design Automation, with an incredible opportunity.
It was a combination of simulation, gate-level speed, and behavioral coding for synthesis that allowed the language to gain an early footing in this space. Designers were excited about the speed-up in simulation, yet the long-term promise of synthesis was also appealing.
From there, gaining ASIC sign-off capability let it and the Verilog simulator consolidate a strong position in the market, as well as provide a well-rounded solution for hardware designers. In a later version, we added more comprehensive timing support, as demanded by the ASIC vendors. This made it more universal in its application.
I'm often asked how in the world I became a designer of HDLs. After giving this question some thought, I have concluded that a language allows an enormous freedom of design choice, making design a mixture of art and science. I relish this balance.
A language designer bridges the gap between the simple constructs that must be manipulated and the tools, which are usually highly complex in nature. Mapping clear language concepts to complex algorithms takes years of effort to understand. I got into this field after working on both hardware and software projects, and found that combining the two could produce fascinating results. Hardware simulation was a natural choice for me.
It's easy to design a language that's complex and cumbersome to use. The trick is to provide the freedom without putting up roadblocks. One aspect of staying in the same field for so long is that it offers me a learning process. This is key for language design because I can meet new challenges without repeating easy-to-make mistakes, while focusing on new improvements.
Ultimately, it's not the language, but the tool chain and design flow that are important. The language supplies the user interface to this process. I took construct ideas that worked well in one language—HILO—and expanded on them in Verilog, while rejecting others. This incremental approach to language design is an essential aspect of creating a good modeling medium.
The idea of language evolution is a key ingredient to adoption. This is clearly demonstrated in the manner that Verilog95 was extended to enable the Verilog 2K1 standard, which, in turn, was extended to Accellera's SystemVerilog, a subset of Superlog itself. Much like a Russian doll, if each language can build on the former, a high level of efficiency is introduced to methodology evolution, leading to fast adoption.
