Synthesis Tool Permits Automatic Design Reuse

True, automatic design reuse for designers from the RTL level to the system level is permitted with the eXplorations tool suite, which allows users to quickly explore design space and architectures, reuse components ranging in complexity from simple combinational logic to complex Core/IPs, and synthesize RTL implementations that go directly into industry standard logic-synthesis tools. The suite consists of the eXplorations Compiler, the eXplorations Database, the eXplorations Environment, and the eXplorations Shell, which form a complete methodology for synthesis and verification of complex IC designs. The eXplorations Compiler takes behavioral and RTL descriptions and creates architectures using pre-existing hard or soft IP cores. It automatically selects IPs for reuse from a library, selects architectures that satisfy the design constraints, maps design descriptions to IPs, generates interfaces between IPs and performs interface arbitration.