Design automation has passed through distinct eras in its history, marked largely by seismic shifts in abstraction. The last great shift, back in the 1980s, saw Verilog lose its proprietary status and become open source. That's when the predominant design paradigm moved from gate level to the register-transfer (RT) level. Since then, other improvements in the IC design flow have helped keep design costs more manageable (Fig. 1).
A paradigm shift of similar magnitude is occurring, but it's different in that the shift is going in two directions at once. At process geometries of 90 nm and smaller, complexity is forcing many designers to look to the system level in the front end of the design cycle. Methodologies that enable intellectual-property (IP) reuse have sprung to the fore. Verification methodologies, too, have begun evolving to encompass the system level, with assertions poised to enter the mainstream.
But at the same time, sub-100-nm processes bring a host of issues to the physical design realm. Now, tools and methodologies are appearing in which front-end design has everything to do with the back end.The tidal wave of talk about design for manufacturability (DFM) presages a period in which much emphasis will be placed on what can be done in logical design to favorably influence physical design.
At the 2004 Design Automation Conference, Gartner Dataquest's Chief EDA Analyst Gary Smith likened the EDA industry to an hourglass (Fig. 2). Six months later, that impression of EDA's overall direction has only been reinforced.
Many designers, especially in larger semiconductor houses, are moving up to electronic-system-level (ESL) flows. Simultaneously, many others are being moved to their organizations' back-end CAD operations as those teams grow to face the physical design challenges.
There's little going on in the RTL world these days. Indeed, the large EDA vendors marketing integrated RTL-to-GDSII flows have done a good job of automating the RTL flow. Consensus has rallied around the notion that only integrated tool flows will work well, or perhaps even at all, at 90 nm and below. As a result, RTL has become more or less commoditized, and hence, Smith's hourglass.
But plenty of work is required to build out the "new front end" promised by ESL flows. The next phase in ESL development will focus on a few subsegments: system-level design, behavioral synthesis, and system-level verification.
System-level design tools will address the need of designers to quickly define and analyze entire systems. The key will be the availability of inexpensive yet fast simulators, such as the free SystemC simulator from OSCI.
Transaction-level modeling (TLM) lets designers evaluate system architecture using a comprehensive virtual prototype, permitting more freedom for architectural exploration than RTL-based approaches. TLM will find acceptance among designers who have flirted with design failure due to over-reliance on RTL-based approaches.
Another ESL design category to watch in 2005 is C-based synthesis, the missing link between algorithmic modeling and physical implementation. After a period of pilot projects and reference-design reviews, 2005 will be the year that C-based synthesis enters the mainstream.
On the back end, DFM will migrate from concerns dominated by transistor-level, after-the-fact manipulation of mask data using resolution enhancement technology (RET) to a more holistic view. At 65 nm, even the more spacious interconnect metal layers will need special steps to improve yield. In both transistor layers and wiring layers, more emphasis will be on enhancing yield early in the design process.
True DFM takes information from the manufacturing process that defines what will and will not result in yield. As more and more designers become responsible for making decisions that affect yield, the industry will move toward a design-centric view of DFM.
