CPLDs Post Major Gains In Macrocell Count And Features

Dec. 1, 2001

Completing the companyÕs second generation of Big-Fast-Wide (BFW) complex programmable logic devices (CPLDs), the ispMACH 5000VG SuperBIG CPLD family doubles the logic capacity and adds a number of new features to the lineÕs previous ispLSI 5000VE family. The ispMACH 51024VG, the first member of the new in-system programmable (ISP) logic family, boasts of 1,024 macrocells, two sysCLOCK phase locked loops (PLLs) to improve high-speed system performance, and sysIO advanced I/O support to help move signals on- and off-chip at high speeds. The device also posts pin-to-pin logic delay times (tPD) of 5 ns with an operating frequency (fMAX) of 178 MHz.With its SuperBIG CPLD architecture supporting system-level integration, the new device also offers 68 inputs to logic blocks and up to 160 product terms per output, thereby helping deliver major increases in system performance. Listed among the CPLDÕs ease-of-use features are predictable deterministic timing, ÒinstantÓ logic availability at power-up, and IEEE 1149.1 boundary scan test support. The 3.3V ispMACH 51024VG is supported by various design tools, is now available in 484- and 676-ball fine-pitch BGAs, and costs as little as $50 each in high volumes, with production set for Q2 of 2002. LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (503) 268-8000.

Sponsored Recommendations


To join the conversation, and become an exclusive member of Electronic Design, create an account today!