SystemVerilog Supports Verification

June 1, 2003

To enable an advanced design-for-verification (DFV) methodology, Synopsys has announced broad support for the Accellera SystemVerilog language. By integrating verification throughout the development process, designers can improve quality and productivity. These gains result from advanced verification technologies, such as assertion-based verification, constraint random-test generation, and formal analysis. Coupled with SystemVerilog, the Synopsys DFV technologies create an approach that enables verification throughout the design flow. One of Synopsys' DFV technologies is a hybrid formal RTL verification product called Magellan. It is integrated with Synopsys' Discovery Verification Platform to further strengthen the DFV methodology.

Synopsys 700 E. Middlefield Rd., Mountain View, CA 94043; (650) 584-5000, www.synopsys.com.

About the Author

John Blyler

John Blyler has more than 18 years of technical experience in systems engineering and program management. His systems engineering (hardware and software) background encompasses industrial (GenRad Corp, Wacker Siltronics, Westinghouse, Grumman and Rockwell Intern.), government R&D (DoD-China Lake) and university (Idaho State Univ, Portland State Univ, and Oregon State Univ) environments. John is currently the senior technology editor for Penton Media’s Wireless Systems Design (WSD) magazine. He is also the executive editor for the WSD Update e-Newsletter.

Mr. Blyler has co-authored an IEEE Press (1998) book on computer systems engineering entitled: ""What's Size Got To Do With It: Understanding Computer Systems."" Until just recently, he wrote a regular column for the IEEE I&M magazine. John continues to develop and teach web-based, graduate-level systems engineering courses on a part-time basis for Portland State University.

John holds a BS in Engineering Physics from Oregon State University (1982) and an MS in Electronic Engineering from California State University, Northridge (1991).