SoC Verification Environment Allows Configurable HDL Checks

March 4, 2002
A new version of the Verification Navigator Integrated Design Verification Environment features significant enhancements to the VN-Check Configurable HDL Checker, the VN-Cover Coverage Analysis solution, and the VN-Control Application-Specific...

A new version of the Verification Navigator Integrated Design Verification Environment features significant enhancements to the VN-Check Configurable HDL Checker, the VN-Cover Coverage Analysis solution, and the VN-Control Application-Specific Test Automation solution.

VN-Check is a configurable HDL checker that lets users organize checks into rule sets. This supports fast, targeted analysis of specific design characteristics such as finite state machines (FSMs), design-for-test, or design-for-reuse. VN-Check now includes mixed Verilog and VHDL dual language support, Verilog IEEE 1364-2001 language support, and enhanced run-time and memory performance.

The VN-Cover 2002.1 coverage analysis tool features a new, exclusive FSM path metric as well as support for 64-bit simulation platforms. The tool's FSM path coverage metric accelerates verification and analysis of complex control blocks based on FSMs. It is also the first and only full-featured coverage analysis solution for Model Technology's 64-bit simulator.

VN-Control is an application-specific test automation tool that works with TransEDA's Foundation Models Verification IP to enable ready-to-use automatic test generation and results checking from a high-level test template. VN-Control 2002.1 is fully integrated into the Verification Navigator environment.

VN-Cover starts at $20,000 for a perpetual license. VN-Check starts at $20,000 for a perpetual license. VN-Control starts at $5000 for an annual subscription license. All tools are available immediately.

TransEDA
(408) 335-1300; www.transeda.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

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