For some time now, advocates of various high-level design languages have sparred over which approach to design at a level of abstraction above register transfer level (RTL) might be best. Many of these approaches have centered on C/C++-based languages. The one that seems to have staying power—and support—is SystemC.
SystemC had initially been touted as a technique for actual hardware design. But designers have taken a wait-and-see approach to hardware design at the algorithmic level that's represented by SystemC. Modeling of hardware in C only takes one so far along the implementation path.
Under the auspices of the Open SystemC Initiative (OSCI), an industry consortium comprising entities from industry and academia, SystemC has drawn a fair share of support nonetheless. When you frame the notion of algorithmic-level design work as a means of exploring architectural tradeoffs, SystemC begins to make more sense. There the use of transaction-level modeling can make a big difference in verification efforts. Some designers will stick to Verilog, especially now that SystemVerilog has incorporated C/C++ algorithmic constructs.
At this June's Design Automation Conference (DAC) in New Orleans, the SystemC Technology Symposium drew about 300 attendees, representing an almost 200% increase from the same event at DAC in 2001. Meanwhile, a new book on SystemC was hot at DAC. Carl W. Harris, publishing director at Kluwer Academic Publishers, reports that its new title, System Design with SystemC, was Kluwer's "runaway bestseller" at the show.
According to OSCI's president, Kevin Kranen of Synopsys Inc., responses to a SystemC survey at DAC revealed that interest in the language is coming from a broad industry cross section. It spans semiconductors, IP providers, and embedded system houses, among others. SystemC is finding use throughout the high-level part of the design flow, from specification to golden-model generation, algorithm definition, hardware/software coverification, and software development partitioning.
More than 66% of the nearly 200 survey participants found SystemC to be from "adequate" to "very good" for verification, while over 75% put it in that range for design work. Yet when asked what's needed to spur growth in the language's use, respondents cited a path to automatic design implementation, integration with design flows based on hardware description language (HDL), and perhaps most importantly, more tools that employ SystemC.
On that latter score, progress is being achieved. OSCI counts 32 SystemC-oriented EDA products on the market. Announcements of tool support have come from industry leaders like Synopsys, Cadence, and Mentor Graphics, as well as others in niche areas, such as CoWare, Verisity, AXYS Design, Prosilog, and LISATek. Interestingly, Anadigm is looking at SystemC for high-level design work using its field-programmable analog arrays.
Integration of SystemC into HDL-based flows is accelerating. Many verification vendors have launched tools that offer mixed-mode simulation of SystemC, Verilog, and VHDL. OSCI's Verification Working Group is hard at work on a new spec for verification extensions to SystemC. At DAC, Fujitsu also presented its success story of LSI design implementing SystemC, detailing its speedup in hardware/software coverification from using SystemC versus a VHDL simulator.
So while designers' willingness to move up in abstraction remains to be seen, the pieces for doing so are slowly but surely coming together.
