The Top 10 Things Designers Don’t Know About Assertion-Based Verification (But Should)

Sept. 16, 2002
10. Assertions give you more time to goof off and read golf magazines while your boss isn't looking. That is, they reduce simulation debug time by 50%. 9. Assertions provide a common...
10. Assertions give you more time to goof off and read golf magazines while your boss isn't looking. That is, they reduce simulation debug time by 50%.9. Assertions provide a common language to use when specifying IP functionality, as nobody in this industry seems to know English that well. Assertion-based verification simplifies IP integration by capturing design intent in a form that permits self-checking code.8. Assertions enable you to see clearly and without obstruction just how crummy your design really is. Assertion-based verification supports white-box verification strategies, which improve observability coverage during verification.7. Assertions are perfect for you control freaks out there. Assertion-based verification addresses the inherent controllability coverage limitations of simulation by enabling adoption and use of emerging semi-formal and formal technologies.6. Assertions are sweet. Accellera's Sugar formal property language supports top-down (functional specification-driven) design methodologies and is well suited for specifying architectural and global properties within an assertion-based verification framework.5. Sugar assertions have fewer calories. Accellera's Sugar formal property language is well suited for defining interface specification during block-level partitioning.4. Taste like chicken. Accellera's SystemVerilog assertion construct facilitates expressing assertions procedurally during RTL development, enabling bottom-up verification practices. 3. Even my mother could understand them. Accellera's Open Verification Library (OVL) provides a template to structurally express a broad class of assertion within the designer's RTL. Also, the July release of the OVL will unify the Accellera Sugar formal property language and the new SystemVerilog procedural form of specification, encapsulated directly within the library components.2. One size fits all The OVL monitors address assertion-based methodology considerations by providing uniformity and predictability, such as: (a) a unified, systematic method of reporting that can be customized per project, (b) a common mechanism for enabling and disabling assertions during the verification process, and (c) a systematic way to filter the reporting of a specific assertion violation by limiting the firing report to a configurable amount.1. Smart engineers already know about assertion-based verification and don't need this list.

Harry Foster is chief architect at Verplex Systems Inc., Milpitas, Calif. He wrote the initial version of the Open Verification Library while at Hewlett-Packard and is currently chairman of Accellera's Formal Property Language Technical Committee.

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