While electronic-system-level (ESL) methodologies continue to be a hot discussion topic, the fact remains that an implementation flow from high-level design to silicon has yet to arrive. As a result, actual adoption of ESL design is at a standstill. But the latter part of 2003 debuted a number of tools that help bridge the gaps in abstraction between C/C++ transaction-level models and timed register-transfer-level (RTL) representations.
The EDA industry, in a somewhat halting manner, is at least making strides toward an ESL implementation flow. With further adoption of SystemC for ESL design work, look for more tools in 2004 that will further serve to fill the void between transaction-level modeling and the RTL flow that must, at least for now, continue to be the path to a gate-level netlist. The drive toward ESL implementation is a Holy Grail of sorts. Even when a viable tool flow becomes available, EDA vendors will have their work cut out for them in terms of overcoming designers' cultural biases and natural suspicion of such a flow.
The traditional implementation flow is seeing some upheaval of its own, driven largely by the broad acceptance of virtual silicon prototyping and automated design-rule checking. Together, these technologies are driving designers toward RTL design handoff to foundries instead of a gate-level netlist handoff. With a plethora of front-end design-planning tools available, designers can identify and repair problems before they go through lengthy and expensive synthesis/place-and-route iteration loops. This can mean optimized designs, quicker design closures, and less need for RTL designers to become experts in place and route.
Timing analysis, which had been relegated to gate-level design, is now moving up into the RTL domain. In the past, timing analysis was largely handled in synthesis or physical synthesis, but taking it to RTL can flag problems that can bog down implementation.
In addition, change is swirling around chip implementation. For many designers, standard-cell-based and custom ASICs are giving way to FPGAs and the upstart structured ASICs now available from numerous vendors. In mid-level and even some higher-volume applications, FPGAs are sneaking into ASIC territory. Why? Simply because FPGA processes and unit costs are coming down even as the mask costs for ASICs escalate. ASIC-like design flows for FPGAs are making it easier than ever for designers to implement very complex functionality on FPGAs.
Likewise, cost is the driver behind the growing acceptance of structured ASICs. They might also fall prey to the wave of FPGA design starts.
TOP TEN- EMBEDDED SoC PROTOTYPING flows using multiple FPGAs will become the norm in larger design houses. The time and money costs of mask re-spins are becoming too high to risk a complex project without building a prototype.
- STRUCTURED ASICs HAVE stormed the market, with growth expected to explode from the $5.2 million in 2002 to $460.3 million in 2007. Look for more tools tailored for structured ASICs.
- EMBEDDED PROCESSORS are appearing on more FPGAs, with soft processors looking like winners over hard cores. There are significant EDA-related problems in assembling such systems, as well as in debugging designs with multiple embedded processors. We'll see tools begin to incorporate capabilities to overcome these issues.
- A STRONGER APPETITE for automated and accelerated analog circuit migration is expected, leading to a substantial reduction (or even elimination) of the current manual process migration job. The digital and memory portions dictate that the chip be implemented in the newest technology, and that includes the analog portions.
- METHODOLOGIES will combine design, manufacturing, and test information to accelerate the ramp-up to acceptable silicon yields. Reticle enhancement techniques, such as model-based optical-proximity correction and phase-shifting mask techniques, have been adopted. Although yield traditionally is viewed as a manufacturing issue, it also has turned into a design issue.
- ON-CHIP PROCESS VARIATION threatens to upset long-standing design and verification methodologies. New tools (such as statistical static-timing analysis), libraries (multidimensional models), and methods (multicorner verification) are needed in this arena.
- ASIC NRE costs are climbing as ASIC technologies advance. The number of design starts for FPGAs is steadily increasing, even through the recent economic downturn, while the opposite is true for ASICs. Complex FPGAs will be used more extensively for prototypes and early production and even for full production.
- THANKS TO SHRINKING silicon processes, lithography will have greater effect on design rules. Routers and/or post-processing tools will begin to carry greater understanding of yield and manufacturability issues.
- PHASE-SHIFTING mask techniques weren't a concern for place-and-route tools at 130 nm. Their impact is arguable at 90 nm. But such techniques will be essential at 65 nm. Placement tools that carry the ability to recognize phase shifts and place cells accordingly will appear.
- BLOCK-BASED PLACEMENT methodologies could find their way into the mainstream. Such divide-and-conquer strategies remove the problems associated with multi-place-and-route-region implementation, with results similar to those achieved in flat design methodologies. Cross-block, full-chip optimization tools are beginning to appear.
