First Steps Taken On Road To C Synthesis

March 29, 2004
Following on the heels of its technology announcement late in 2003, Synfora is now shipping PICO Express, its algorithm-to-tapeout tool that synthesizes C algorithms into Verilog RTL. With the tool's release comes more information on the technology...

Following on the heels of its technology announcement late in 2003, Synfora is now shipping PICO Express, its algorithm-to-tapeout tool that synthesizes C algorithms into Verilog RTL. With the tool's release comes more information on the technology and what it can and can't do, as well as hints about future directions.

PICO Express is intended for use with compute-intensive algorithms, particularly with nested for-loops. The tool first verifies that the designer's code, which is usually derived from a reference algorithm such as MPEG-2 or -4 decoding, can generate efficient hardware. Once verified, the tool's compiler creates a series of pipeline processor arrays (PPAs).

It begins by finding the maximum amount of parallelism at the loop and instruction levels, performing optimizations and inserting software pipelining. Next, it examines the designer-specified performance requirements to determine the hardware resources it will need to achieve those goals. Finally, it schedules operations in time, after which it can allocate resources and map to Synfora's macro library. The library is characterized for TSMC's 0.13-µm process technology.

Certain coding requirements must be met for PICO Express to do its magic, though. Most importantly, the use of pointers and aliasing isn't permitted within the algorithm. "Software coders get upset at this," says Vinod Katthail, Synfora's founder and CTO. "But hardware designers won't mind. There's no pointers in RTL." The goal of Synfora's technology is to get RTL designers to move up to C, so the pointer restriction shouldn't be an issue for the target audience.

In an ASIC design flow, PICO Express requires the C program code, a data set, and system requirements such as bandwidth, clocking, latency, and area (see the figure). The other input is the macro library, which enables the tool to calculate area and performance. The tool delivers the RTL for the algorithm, synthesis scripts for Design Compiler and Physical Compiler, and a testbench.

"This is only the first step," says Simon Napper, Synfora's CEO. "It'll take years to move hardware designers up to C, and accelerators are a starting point." The next step might be a nonprogrammable accelerator for a much wider subset of the C language. After that, the goal would be to move to programmable functions.

Available now, PICO Express costs $125,000 for a design project license.

Synfora Inc.www.synfora.com
About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!