First Commercial Parser Ships For System Verilog

Nov. 29, 2004

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial availability of a parser for the language....

David Maliniak

Verific Design Automation's SystemVerilog parser has already seen early adoption in formal verification and HDL visualization tools. It lets EDA tool developers support SystemVerilog within their tools. And, it's apt to spur quicker adoption of the language.

Written in C++ for easy integration into existing EDA tools, the parser includes an analyzer and elaborator. It parses and analyzes the entire SystemVerilog 3.1 language definition with the exception of SystemVerilog Assertions, for which it follows the SystemVerilog 3.1a syntax. After parsing, a complete parse tree is available.

Static elaboration and register-transfer-level (RTL) elaboration for synthesis is fully supported for the Verilog 2001 subset and is extended with support for many of the new SystemVerilog constructs. Verific plans additional elaboration for intermediate releases between now and the end of this year.

The parser has been tested with an internally developed SystemVerilog test suite. It also has been verified with simulators provided by partnerships with Synopsys and Mentor Graphics.

Verific's SystemVerilog parser is available now. It runs on Solaris, HP-UX, Linux, and Windows platforms. Pricing starts at $100,000 for a perpetual, royalty-free source code license for the parser and analyzer. Time-based licenses start at $4000 per month.

Verific Design Automationwww.verific.com

See associated figure

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.