The Keys To Achieving Power Integrity

Feb. 3, 2005
Understanding the factors that account for total IC power consumption is crucial when designing a modern, power-efficient chip. As a designer, you must strike a balance among design styles, available IP choices, and process and manufacturing opt

Understanding the factors that account for total IC power consumption is crucial when designing a modern, power-efficient chip. As a designer, you must strike a balance among design styles, available IP choices, and process and manufacturing options to satisfy the power requirements of your final system.

TIP 1: CHOOSE THE RIGHT IP LIBRARY AND PROCESS VARIANT. Choosing a technology node, process variant, and IP library can be daunting for nearly any design team, yet these factors exert an influence on power integrity that can't be overstated. One must select from literally dozens of available cell libraries and process variants in each technology node. With IP standard cell and memory libraries varying up to 20 times in power and leakage, without even factoring in process variants, it's absolutely essential to understand which is ideal for a given design.

Early exploration of these options helps determine the right set of parameters to optimize the areas of interest for your design. Consider investing in a design planning tool that lets you visualize the impact of varying libraries and manufacturing options, or take a medium-sized design block through an implementation flow. Lower power or leakage typically comes at the cost of performance and area, so understanding the magnitude of these tradeoffs is key. Make certain to also factor in any economic impact, such as higher wafer costs for exotic processes and NREs associated with power or leakage optimized IP libraries.

TIP 2: UNDERSTAND THE BREAKDOWN OF POWER. Using a power-centric approach to floorplanning can greatly improve power integrity. When considering power density, which varies across different design structures, ask yourself which structures will dominate which effects. Standard cells are dominated by wire power, memories by transistor density and size, and I/Os by type and external loading. IP structures can be mixed. Such an understanding can help you determine where to most effectively employ advanced power-centric design and floorplanning strategies, such as gated clocks, lowering activities, and controlling loads, to minimize power of high-density elements.

Different logic blocks within a design also will vary in power density, based on different operating frequencies and switching activities. Strategies such as keeping higher power and noisy blocks near the I/O pads, and providing extra area for bypass capacitors around power-hungry structures, can further optimize a floorplan for power integrity. Also, perform iterative bottom-up analysis, first at the block level, then across the entire die, to balance power across a design. Finally, consider using multiple-cell libraries, varying threshold voltages, and creating selective power-down voltage islands to further reduce power consumption.

TIP 3: CONSIDER ARCHITECTURAL DESIGN TRADEOFFS. Often, it's useful to take a step back and consider high-level architectural design tradeoffs to improve power integrity. Changing the core design specification may still allow you to meet feature and performance goals while minimizing power. One simple way to conserve power as well as die area is to implement functions in software rather than in application-specific hardware. This tactic makes particularly good sense in large system-on-a-chip designs that might contain one or more processors with extra cycles.

Another common architectural tradeoff is to move energy-hungry or power-disruptive components—for example, large memories and analog circuitry—off-chip. The physical relocation will not only reduce risk to nearby components, it may also help avoid expensive ceramic packages. Another tactic entails embedding noisy analog circuitry within the I/O ring, where it can be effectively shielded and thus have less effect on core digital logic. This I/O ring-embedding tactic has the added benefit of helping reduce core die area in core-bound designs.

With design teams becoming increasingly focused on chip power, it makes sense to spend time early in the design flow to perform analysis of IP, manufacturing, and architectural tradeoffs to minimize power and leakage and to ultimately improve power integrity. If you remain uncertain, consulting an expert early in the design cycle can help you understand these and other options available to you.

Sponsored Recommendations

TTI Transportation Resource Center

April 8, 2024
From sensors to vehicle electrification, from design to production, on-board and off-board a TTI Transportation Specialist will help you keep moving into the future. TTI has been...

Bourns: Automotive-Grade Components for the Rough Road Ahead

April 8, 2024
The electronics needed for transportation today is getting increasingly more demanding and sophisticated, requiring not only high quality components but those that interface well...

TTI Rail Transit Line Card

April 8, 2024
TTI stocks premier interconnect, passive and electromechanical components for rail systems as diverse as door control, HVAC and cabin entertainment, trackside safety, communications...

Littelfuse: Take Charge for Peak Performance in Material Handling Evs

April 8, 2024
As material handling electric vehicles such as automated guided vehicles (AGVs), autonomous mobile robots (AMRs) and forklifts become an integral part of Industry 4.0, Littelfuse...


To join the conversation, and become an exclusive member of Electronic Design, create an account today!