Electronic Design
  • Resources
  • Directory
  • Webinars
  • CAD Models
  • Video
  • Blogs
  • More Publications
  • Advertise
    • Search
  • Top Stories
  • Tech Topics
  • Analog
  • Power
  • Embedded
  • Test
  • AI / ML
  • Automotive
  • Data Sheets
  • Topics
    - TechXchange Topics --- Markets --AutomotiveAutomation-- Technologies --AnalogPowerTest & MeasurementEmbedded
    Resources
    Electronic Design ResourcesTop Stories of the WeekNew ProductsKit Close-UpElectronic Design LibrarySearch Data SheetsCompany DirectoryBlogsContribute
    Members
    ContentBenefitsSubscribeDigital editions
    Advertise
    https://www.facebook.com/ElectronicDesign
    https://www.linkedin.com/groups/4210549/
    https://twitter.com/ElectronicDesgn
    https://www.youtube.com/channel/UCXKEiQ9dob20rIqTA7ONfJg
    1. News
    2. Products

    Low-Power Design Techniques Drop 90-nm Consumption

    April 14, 2005
    Power management is fast becoming one of the most critical design constraints in the world of IC designers. New 90-nm processes deliver greater silicon performance and integration, but battery technology hasn't kept up. To compensate, new design tec
    David Maliniak

    Power management is fast becoming one of the most critical design constraints in the world of IC designers. New 90-nm processes deliver greater silicon performance and integration, but battery technology hasn't kept up. To compensate, new design techniques are being developed to address the need for low-power silicon.

    A collaboration between members of the Silicon Design Chain (Applied Materials, ARM, Cadence, and TSMC) has resulted in a demonstration of the ARM1136JF-S core module as part of an effective power-management system. The ARM1136 was chosen because of its wide application in wireless systems.

    The design flow used TSMC's 90-nm G process, Artisan physical IP, including SAGE-X memories and standard cells, and a production Cadence Encounter design platform. In the flow, power was attacked on two fronts: leakage and dynamic power.

    Use of ARM/Artisan physical IP was the main weapon against leakage. The team used libraries that contained a matched set of logic cells, each having different threshold voltages (VT) and the same physical footprint. The cells with the higher threshold voltages leak less than their lower-VT counterparts. The Encounter synthesis tool devised a netlist that met the desired 350-MHz performance goal with the lowest possible leakage current.

    On the dynamic-power side, voltage scaling was applied to segments of the design that were deemed noncritical for performance. Timing-critical segments were kept at a 1-V supply while less timing-critical blocks were scaled back to 0.8 V, saving 36% of dynamic power for that portion of the design. To achieve this voltage reduction, 3400 level shifters were automatically inserted.

    Further power reduction was accomplished through clock gating. The Cadence tools were used to automate clock gating. Additionally, some minor adjustments were made to the Cadence Encounter flow to achieve the group's goals. Those adjustments will be incorporated into the 4.2 release of the Encounter platform, which should be available now.

    Silicon Design Chain Initiativewww.silicondesignchain.com

    Continue Reading

    Sponsored Recommendations

    Take Charge with Littelfuse Charging Solutions for Peak Performance in Material Handling EVs

    Nov. 28, 2023

    Nexperia Webinar: Application Specific MOSFETs and GaN Solutions for the Automotive Market

    Nov. 28, 2023

    TTI Transportation Resource Center

    Nov. 28, 2023

    Molex: What Happens When the Driver’s Seat is Empty?

    Nov. 28, 2023

    Comments

    To join the conversation, and become an exclusive member of Electronic Design, create an account today!

    I already have an account

    New

    Automotive-Rated Dual Op Amp Blends Medium Voltage and Accuracy

    How to Build Wide-Dynamic-Range Systems (Part 1)

    Bob Pease on Analog Vol. 3

    Most Read

    Non-Metallic Gigahertz Antenna Built with Laser and Glass Cell

    MEMS Mirrors: The Next Big Wave in MEMS Technology

    Useful Trustworthy AI Sensors in Tiny Packages


    Sponsored

    Signal Chain Power (SCP) Hardware Evaluation Platform

    Power Products

    How processing in real-time drives high-performance power systems

    Electronic Design
    https://www.facebook.com/ElectronicDesign
    https://www.linkedin.com/groups/4210549/
    https://twitter.com/ElectronicDesgn
    https://www.youtube.com/channel/UCXKEiQ9dob20rIqTA7ONfJg
    • About Us
    • Contact Us
    • Advertise
    • Do Not Sell or Share
    • Privacy & Cookie Policy
    • Terms of Service
    © 2023 Endeavor Business Media, LLC. All rights reserved.
    Endeavor Business Media Logo